DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER

FEATURES · Operates From 1.65 V to 3.6 V · Inputs Accept Voltages to 5.5 V · Max tpd of 6.2 ns · Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C · Latch-Up Performance Exceeds 250 mA Per JESD 17 ·

封装/外壳：16-VFQFN 裸露焊盘 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DECODER/DEMUX 1X2:4 16VQFN 集成电路（IC） 信号开关，多路复用器，解码器

DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER

文件：346.3 Kbytes Page：15 Pages

DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER

文件：1.40274 Mbytes Page：30 Pages

DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER

文件：856.5 Kbytes Page：20 Pages

DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER

FEATURES · Operates From 1.65 V to 3.6 V · Inputs Accept Voltages to 5.5 V · Max tpd of 6.2 ns · Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C · Latch-Up Performance Exceeds 250 mA Per JESD 17 ·

DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER

FEATURES · Operates From 1.65 V to 3.6 V · Inputs Accept Voltages to 5.5 V · Max tpd of 6.2 ns · Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C · Latch-Up Performance Exceeds 250 mA Per JESD 17 ·

DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER

文件：856.5 Kbytes Page：20 Pages

DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER

文件：1.40274 Mbytes Page：30 Pages

Dual 2-to-4 line decoder/demultiplexer

DESCRIPTION The 74LVC139 is a low-voltage, low-power, high-performance Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5 V • CMOS lo

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74LVC139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4 demulti

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74LVC139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4 demulti

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74LVC139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4 demulti

Dual 2-to-4 line decoder/demultiplexer

DESCRIPTION The 74LVC139 is a low-voltage, low-power, high-performance Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5 V • CMOS lo