SN74LV165B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Supports mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 • Operating ambient temperature: -55°C to +125°C • Supports defe

SN74LV165B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Supports mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 • Operating ambient temperature: -55°C to +125°C • Supports defe

SN74LV165B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Supports mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 • Operating ambient temperature: -55°C to +125°C • Supports defe

SN74LV165B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Supports mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 • Operating ambient temperature: -55°C to +125°C • Supports defe

8-bit parallel-in/serial-out shift register

1. General description The 74LV165 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 i

8-bit parallel-in/serial-out shift register

1. General description The 74LV165A is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel-load input (PL) is LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously. W

8-bit parallel-in/serial-out shift register

文件：137.66 Kbytes Page：14 Pages

8-bit parallel-in/serial-out shift register

文件：102.57 Kbytes Page：18 Pages

PARALLEL-LOAD 8-BIT SHIFT REGISTERS

文件：735.4 Kbytes Page：19 Pages