DUAL J-K FLIP-FLOPS WITH CLEAR

Package Options Include Plastic ‘*Small Outline’” Packages, Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description The ‘73, and 'H73, contain two independent JK flip-flops with individual J-K, clock, and direct clear inputs. The ‘

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF JK TYPE DUAL 1BIT 14SOIC 集成电路（IC） 触发器

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：872.08 Kbytes Page：17 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

Package Options Include Plastic ‘*Small Outline’” Packages, Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description The ‘73, and 'H73, contain two independent JK flip-flops with individual J-K, clock, and direct clear inputs. The ‘

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：872.08 Kbytes Page：17 Pages

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：主复位 包装：卷带（TR） 描述：IC FF JK TYPE DUAL 1BIT 14SOIC 集成电路（IC） 触发器

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

Dual J-K Flip-Flops(with Clear)

Dual J-K Flip-Flops(with Clear)

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：206.08 Kbytes Page：13 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：206.08 Kbytes Page：13 Pages