TRIPLE 3-INPUT NAND GATE

TRIPLE 3-INPUT NAND GATE

3 通道、3 输入、4.75V 至 5.25V 双极与非门

These devices contain three independent 3-input NAND gates.\n\n The SN5410, SN54LS10, and SN54S10 are characterized for operation over the full military temperature range of –55°C to 125°C. The SN7410, SN74LS10 and SN74S10 are characterized for operation from 0°C to 70°C. • Package Options Include Plastic \"Small Outline\" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs\n• Dependable Texas Instruments Quality and Reliability;

TRIPLE 3-INPUT NAND GATE

TRIPLE 3-INPUT POSITIVE-NAND GATES

文件：935.34 Kbytes Page：19 Pages

TRIPLE 3-INPUT POSITIVE-NAND GATES

文件：597.95 Kbytes Page：14 Pages

丝印代码：SN74LS107AN；DUAL J-K FLIP-FLOPS WITH CLEAR

Package Options Include Plastic ‘*Small Outline’* Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description The 107 contain two independent JK flip-flops with individual JK, clock, and direct clear inputs. The ‘107 is

丝印代码：SN74LS107AN；DUAL J-K FLIP-FLOPS WITH CLEAR

Package Options Include Plastic ‘*Small Outline’* Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description The 107 contain two independent JK flip-flops with individual JK, clock, and direct clear inputs. The ‘107 is

丝印代码：SN74LS109AN；DUAL JK POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic “Small Outline’ Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description These devices contain two independent J-K positive- edge triggered flip-flops. A low level

丝印代码：SN74LS109AN；DUAL JK POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic “Small Outline’ Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description These devices contain two independent J-K positive- edge triggered flip-flops. A low level

丝印代码：SN74LS109AN；DUAL JK POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic “Small Outline’ Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description These devices contain two independent J-K positive- edge triggered flip-flops. A low level

DUAL J-K FLIP-FLOPS WITH CLEAR

Package Options Include Plastic ‘*Small Outline’* Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description The 107 contain two independent JK flip-flops with individual JK, clock, and direct clear inputs. The ‘107 is

丝印代码：LS107A；DUAL J-K FLIP-FLOPS WITH CLEAR

Package Options Include Plastic ‘*Small Outline’* Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description The 107 contain two independent JK flip-flops with individual JK, clock, and direct clear inputs. The ‘107 is

丝印代码：LS107A；DUAL J-K FLIP-FLOPS WITH CLEAR

Package Options Include Plastic ‘*Small Outline’* Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description The 107 contain two independent JK flip-flops with individual JK, clock, and direct clear inputs. The ‘107 is

丝印代码：74LS107A；DUAL J-K FLIP-FLOPS WITH CLEAR

Package Options Include Plastic ‘*Small Outline’* Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description The 107 contain two independent JK flip-flops with individual JK, clock, and direct clear inputs. The ‘107 is

丝印代码：74LS107A；DUAL J-K FLIP-FLOPS WITH CLEAR

Package Options Include Plastic ‘*Small Outline’* Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description The 107 contain two independent JK flip-flops with individual JK, clock, and direct clear inputs. The ‘107 is

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY The SN54/74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOWtransition of the clock. A LOW signal on CD input overrides the other inputs and makes th

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY The SN54/74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOWtransition of the clock. A LOW signal on CD input overrides the other inputs and makes th

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY The SN54/74LS109A consists of two high speed completely independent transition clocked JKflip-flops. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D flip-flop by

LOW POWER SCHOTTKY

LOW POWER SCHOTTKY The SN74LS109A consists of two high speed completely independent transition clocked JKflip-flops.

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic Small Outline Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Depondable Texas Instruments Quality and Reliability

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic Small Outline Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Depondable Texas Instruments Quality and Reliability

DUAL JK POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic “Small Outline’ Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description These devices contain two independent J-K positive- edge triggered flip-flops. A low level

LOW POWER SCHOTTKY

LOW POWER SCHOTTKY The SN74LS109A consists of two high speed completely independent transition clocked JKflip-flops.

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic Small Outline Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Depondable Texas Instruments Quality and Reliability

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic Small Outline Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Depondable Texas Instruments Quality and Reliability

LOW POWER SCHOTTKY

LOW POWER SCHOTTKY The SN74LS109A consists of two high speed completely independent transition clocked JKflip-flops.

丝印代码：LS109A；DUAL JK POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic “Small Outline’ Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description These devices contain two independent J-K positive- edge triggered flip-flops. A low level

丝印代码：LS109A；DUAL JK POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic “Small Outline’ Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description These devices contain two independent J-K positive- edge triggered flip-flops. A low level

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic Small Outline Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Depondable Texas Instruments Quality and Reliability

丝印代码：LS109A；DUAL JK POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic “Small Outline’ Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description These devices contain two independent J-K positive- edge triggered flip-flops. A low level

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic Small Outline Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Depondable Texas Instruments Quality and Reliability

LOW POWER SCHOTTKY

LOW POWER SCHOTTKY The SN74LS109A consists of two high speed completely independent transition clocked JKflip-flops.

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic Small Outline Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Depondable Texas Instruments Quality and Reliability

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic Small Outline Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Depondable Texas Instruments Quality and Reliability

丝印代码：74LS109A；DUAL JK POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic “Small Outline’ Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description These devices contain two independent J-K positive- edge triggered flip-flops. A low level

丝印代码：74LS109A；DUAL JK POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic “Small Outline’ Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description These devices contain two independent J-K positive- edge triggered flip-flops. A low level

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY The SN54/74LS109A consists of two high speed completely independent transition clocked JKflip-flops. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D flip-flop by

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY The SN54/74LS109A consists of two high speed completely independent transition clocked JKflip-flops. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D flip-flop by

TRIPLE 3-INPUT NAND GATE

TRIPLE 3-INPUT NAND GATE LOW POWER SCHOTTKY

TRIPLE 3-INPUT NAND GATE

TRIPLE 3-INPUT NAND GATE LOW POWER SCHOTTKY

TRIPLE 3-INPUT NAND GATE

TRIPLE 3-INPUT NAND GATE LOW POWER SCHOTTKY

TRIPLE 3-INPUT NAND GATE

TRIPLE 3-INPUT NAND GATE LOW POWER SCHOTTKY

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：493.55 Kbytes Page：12 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：841.36 Kbytes Page：16 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：841.36 Kbytes Page：16 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：493.55 Kbytes Page：12 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：493.55 Kbytes Page：12 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：841.36 Kbytes Page：16 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：841.36 Kbytes Page：16 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：493.55 Kbytes Page：12 Pages

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：主复位 包装：卷带（TR） 描述：IC FF JK TYPE DUAL 1BIT 14SOIC 集成电路（IC） 触发器

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：主复位 包装：卷带（TR） 描述：IC FF JK TYPE DUAL 1BIT 14SOIC 集成电路（IC） 触发器

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：493.55 Kbytes Page：12 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：841.36 Kbytes Page：16 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：841.36 Kbytes Page：16 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：841.36 Kbytes Page：16 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：493.55 Kbytes Page：12 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：493.55 Kbytes Page：12 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：841.36 Kbytes Page：16 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：493.55 Kbytes Page：12 Pages

TRIPLE 3-INPUT NAND GATE

Triple 3-Input NAND Gate

Triple 3-Input NAND Gate

Triple 3-Input NAND Gates

Triple 3-Input Positive NAND Gates

Triple 3-input Positive NAND Gates

Ouadruple 2-input Positive NAND Gates

Triple 3-Input Positive NAND Gates