12-BIT ASYNCHRONOUS BINARY COUNTERS

文件：601.73 Kbytes Page：17 Pages

12-BIT ASYNCHRONOUS BINARY COUNTERS

文件：752.59 Kbytes Page：19 Pages

封装/外壳：16-DIP（0.300"，7.62mm） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC ASYNC BINARY COUNTER 16-DIP 集成电路（IC） 计数器，除法器

12-BIT ASYNCHRONOUS BINARY COUNTERS

文件：601.73 Kbytes Page：17 Pages

12-BIT ASYNCHRONOUS BINARY COUNTERS

文件：752.59 Kbytes Page：19 Pages

12-BIT ASYNCHRONOUS BINARY COUNTERS

文件：601.73 Kbytes Page：17 Pages

12-BIT ASYNCHRONOUS BINARY COUNTERS

文件：752.59 Kbytes Page：19 Pages

封装/外壳：16-SOIC（0.209"，5.30mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：LOGIC GATES AND INVERTERS 集成电路（IC） 计数器，除法器

12-BIT ASYNCHRONOUS BINARY COUNTERS

文件：601.73 Kbytes Page：17 Pages

12-BIT ASYNCHRONOUS BINARY COUNTERS

文件：752.59 Kbytes Page：19 Pages

12-BIT ASYNCHRONOUS BINARY COUNTERS

文件：752.59 Kbytes Page：19 Pages

12-BIT ASYNCHRONOUS BINARY COUNTERS

文件：601.73 Kbytes Page：17 Pages

12-BIT ASYNCHRONOUS BINARY COUNTERS

文件：752.59 Kbytes Page：19 Pages

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

12-stage binary ripple counter

1. General description The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stage

High Speed CMOS Logic

Features  Output Drive Capability: 10 LSTTL Loads  Low Input Current: 1μA  Outputs directly interface CMOS, NMOS and TTL  Operating Voltage Range: 2V to 6V  CMOS High Noise Immunity  Function compatible with CD4040B

12-stage binary ripple counter

1. General description The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stage

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr