17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE

Compatible With IEEE Std 1194.1-1991 (BTL) LVTTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA B-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage High-Impedance State During Power Up and Power Down S

17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE

Compatible With IEEE Std 1194.1-1991 (BTL) LVTTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA B-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage High-Impedance State During Power Up and Power Down S

17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE

文件：201.62 Kbytes Page：12 Pages

17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE

Compatible With IEEE Std 1194.1-1991 (BTL) LVTTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA B-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage High-Impedance State During Power Up and Power Down S

17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE

文件：201.62 Kbytes Page：12 Pages