SN54AHCT132, SN74AHCT132 Quadruple Positive-NAND Gates With Schmitt-trigger Inputs

1 Features • Operating range of 4.5 V to 5.5 V • Low power consumption, 10-μA maximum ICC • ±8-mA output drive at 5 V • Operation from very slow input transitions • Temperature-compensated threshold levels • High noise immunity • Same pinouts as ’AHCT00 • Latch-up performance exceeds 250 m

Quad 2-input NAND Schmitt trigger

DESCRIPTION The 74AHC/AHCT132 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT132 contain four 2-input NAND gates which accept standard input signals. They are capable of tr

Quad 2-input NAND Schmitt trigger

1. General description The 74AHC132; 74AHCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. 2. Features and benefits • Wide supply voltage range from 2.0 V t

Quad 2-input NAND Schmitt trigger

1. General description The 74AHC132; 74AHCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. 2. Features and benefits • Wide supply voltage range from 2.0 V t

Quad 2-input NAND Schmitt trigger

1. General description The 74AHC132; 74AHCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. 2. Features and benefits • Wide supply voltage range from 2.0 V t

Quad 2-input NAND Schmitt trigger

DESCRIPTION The 74AHC/AHCT132 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT132 contain four 2-input NAND gates which accept standard input signals. They are capable of tr