SNx4AHCT125 Quadruple Bus Buffer Gates With 3-State Outputs

1 Features • Inputs are TTL-voltage compatible • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Enable or disable a digital signal • Controlling an indicator LED • Debounce a switch • Eliminate slow or noisy input signals 3 Description The ’AHCT125 devices are quadr

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

文件：905.14 Kbytes Page：22 Pages

封装/外壳：14-SOIC（0.209"，5.30mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC BUFFER NON-INVERT 5.5V 14SOP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

文件：926.42 Kbytes Page：20 Pages

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

文件：636 Kbytes Page：18 Pages

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

文件：926.42 Kbytes Page：20 Pages

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

文件：905.14 Kbytes Page：22 Pages

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

文件：1.034349 Mbytes Page：23 Pages

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

文件：1.034349 Mbytes Page：23 Pages

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

文件：905.14 Kbytes Page：22 Pages

Quad buffer/line driver; 3-state

1. General description The 74AHC125; 74AHCT125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs are overvoltage tolerant. This feature allows the use of these devices as

Quad buffer/line driver; 3-state

DESCRIPTION The 74AHC/AHCT125 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT125 are four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) a

Quad buffer/line driver; 3-state

QUADRUPLE 3-STATE BUFFERS OE LOW

Description The 74AHCT125 provides provides four independent buffer gates with 3-state outputs. Each buffer has a separate enable pin that if driven with a high logic level places the corresponding output in the high impedance state. The device is designed for operation with a power supply range

Quad buffer/line driver; 3-state