3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

文件：683.91 Kbytes Page：2 Pages

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

文件：1.3501 Mbytes Page：28 Pages

封装/外壳：16-VFQFN 裸露焊盘 包装：管件 描述：IC DECODER/DEMUX 1X3:8 16VQFN 集成电路（IC） 信号开关，多路复用器，解码器

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74AHC138; 74AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC138; 74AHCT138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary we

3-TO-8 LINE DECODER DEMULTIPLEXER

Description The 74AHC138 is an advanced high speed CMOS device. The device accepts a three bit binary weighted address on input pins A0, A1 and A2 and when enabled will produce one active low output with the remaining seven being high. Features • Wide Supply Voltage Range from 2.0 V to 5.

3-to-8 line decoder/demultiplexer; inverting

DESCRIPTION The 74AHC/AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74AHC138; 74AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC138; 74AHCT138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary we

3-to-8 line decoder/demultiplexer; inverting

DESCRIPTION The 74AHC/AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A