丝印代码：AHC00MEP；QUADRUPLE 2-INPUT POSITIVE-NAND GATE

Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree EPIC (Enhanced-Performance Implanted CMOS) Process O

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

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Quad 2-input NAND gate

DESCRIPTION The 74AHC/AHCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT00 provides the 2-input NAND function. FEATURES • ESD protection: HBM EIA/J

Quad 2-input NAND gate

DESCRIPTION The 74AHC/AHCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT00 provides the 2-input NAND function. FEATURES • ESD protection: HBM EIA/J

Quad 2-input NAND gate

DESCRIPTION The 74AHC/AHCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT00 provides the 2-input NAND function. FEATURES • ESD protection: HBM EIA/J

Quad 2-input NAND gate

DESCRIPTION The 74AHC/AHCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT00 provides the 2-input NAND function. FEATURES • ESD protection: HBM EIA/J