SNx4ACT74 Dual Positive-Edge-Triggered D-Type Flip-Flops

1 Features • 4.5V to 5.5V VCC operation • Inputs accept voltages to 5.5V • Max tpd of 10.5ns at 5V • Inputs are TTL-voltage compatible 2 Description The 'ACT74 dual positive-edge-triggered devices are D-type flip-flops.

SNx4ACT74 Dual Positive-Edge-Triggered D-Type Flip-Flops

1 Features • 4.5V to 5.5V VCC operation • Inputs accept voltages to 5.5V • Max tpd of 10.5ns at 5V • Inputs are TTL-voltage compatible 2 Description The 'ACT74 dual positive-edge-triggered devices are D-type flip-flops.

封装/外壳：14-SOIC（0.209"，5.30mm 宽） 功能：设置（预设）和复位 包装：卷带（TR） 描述：IC FF D-TYPE DUAL 1BIT 14SOP 集成电路（IC） 触发器

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：528.92 Kbytes Page：16 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：1.15348 Mbytes Page：21 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：1.15348 Mbytes Page：21 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：528.92 Kbytes Page：16 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：1.15348 Mbytes Page：21 Pages

Dual D?뭈ype Positive Edge?뭈riggered Flip?묯lop

Dual D−Type Positive Edge−Triggered Flip−Flop The MC74AC74/74ACT74 is a dual D−type flip−flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at

Dual D-Type Positive Edge-Triggered Flip-Flop

General Description The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and i

DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The 74ACT74 is an advanced high-speed CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. A signal on the D INPUT is transferred to the Q and QOUTPUTS during the positive going transition of

Advanced CMOS TTL Input

文件：504.1 Kbytes Page：6 Pages

Dual D-Type Positive Edge-Triggered Flip-Flop

文件：111.59 Kbytes Page：10 Pages