丝印代码：AD533；OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 11 ns at 5 V Inputs Are TTL-Voltage Compatible 3-State Inverting Outputs Drive Bus Lines Directly description/ordering information The ’ACT533 devices are octal transparent D-type latches with 3-state outputs. When t

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC OCT TRNSP D-TYP LATCH 20TSSOP 集成电路（IC） 锁存器

丝印代码：AD533；OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 11 ns at 5 V Inputs Are TTL-Voltage Compatible 3-State Inverting Outputs Drive Bus Lines Directly description/ordering information The ’ACT533 devices are octal transparent D-type latches with 3-state outputs. When t

Octal Transparent Latch with 3-STATE Outputs

General Description The ACT533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus

Octal Transparent Latch with 3-STATE Outputs

General Description The ACT533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus

Octal Transparent Latch with 3-STATE Outputs

General Description The ACT533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus

Octal Transparent Latch with 3-STATE Outputs

General Description The ACT533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus

OCTAL TRANSPARENT LATCH, 3-STATE

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