9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

9-bit interface latch with set and reset 3-State

DESCRIPTION The 74ABT843 Bus interface latch is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Extra data width for wide address/data pat

9-bit interface latch with set and reset 3-State

DESCRIPTION The 74ABT843 Bus interface latch is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Extra data width for wide address/data pat

9-bit interface latch with set and reset 3-State

DESCRIPTION The 74ABT843 Bus interface latch is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Extra data width for wide address/data pat

9-bit interface latch with set and reset 3-State

DESCRIPTION The 74ABT843 Bus interface latch is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Extra data width for wide address/data pat

9-bit interface latch with set and reset 3-State

DESCRIPTION The 74ABT843 Bus interface latch is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Extra data width for wide address/data pat