SN65LVDS822 Flatlink™ LVDS Receiver

1 Features 1• 4:27 LVDS-to-CMOS Deserializer • Pixel Clock Range of 4 MHz to 54 MHz, for Resolutions of 160 × 120 to 1024 × 600 • Special 2:27 Mode With 14x Sampling Allows Using Just Two Data Lanes • Very Low EMI With 3-Way Selectable CMOS Slew Rate • Supports Single 3.3-V Power Supply; V

FLATLINK LVDS RECEIVER

文件：418.52 Kbytes Page：27 Pages

封装/外壳：48-VFQFN 裸露焊盘 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC RECEIVER 0/4 48VQFN 集成电路（IC） 驱动器，接收器，收发器

SN65LVDS822 Flatlink™ LVDS Receiver

1 Features 1• 4:27 LVDS-to-CMOS Deserializer • Pixel Clock Range of 4 MHz to 54 MHz, for Resolutions of 160 × 120 to 1024 × 600 • Special 2:27 Mode With 14x Sampling Allows Using Just Two Data Lanes • Very Low EMI With 3-Way Selectable CMOS Slew Rate • Supports Single 3.3-V Power Supply; V

FLATLINK??LVDS RECEIVER

文件：965.04 Kbytes Page：30 Pages

FLATLINK LVDS RECEIVER

文件：418.52 Kbytes Page：27 Pages

SN65LVDS822 Flatlink™ LVDS Receiver

1 Features 1• 4:27 LVDS-to-CMOS Deserializer • Pixel Clock Range of 4 MHz to 54 MHz, for Resolutions of 160 × 120 to 1024 × 600 • Special 2:27 Mode With 14x Sampling Allows Using Just Two Data Lanes • Very Low EMI With 3-Way Selectable CMOS Slew Rate • Supports Single 3.3-V Power Supply; V

SN65LVDS822 Flatlink™ LVDS Receiver

1 Features 1• 4:27 LVDS-to-CMOS Deserializer • Pixel Clock Range of 4 MHz to 54 MHz, for Resolutions of 160 × 120 to 1024 × 600 • Special 2:27 Mode With 14x Sampling Allows Using Just Two Data Lanes • Very Low EMI With 3-Way Selectable CMOS Slew Rate • Supports Single 3.3-V Power Supply; V

SN65LVDS822 Flatlink™ LVDS Receiver

1 Features 1• 4:27 LVDS-to-CMOS Deserializer • Pixel Clock Range of 4 MHz to 54 MHz, for Resolutions of 160 × 120 to 1024 × 600 • Special 2:27 Mode With 14x Sampling Allows Using Just Two Data Lanes • Very Low EMI With 3-Way Selectable CMOS Slew Rate • Supports Single 3.3-V Power Supply; V