功能：LVDS，缓冲器/中继器 包装：散装 描述：EVALUATION MODULE FOR SN65LVDS19 开发板，套件，编程器 评估和演示板及套件

2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS

FEATURES · Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs · Clock Rates to 1 GHz – 250-ps Output Transition Times – 0.12 ps Typical Intrinsic Phase Jitter – Less than 630 ps Propagation Delay Times · 2.5-V or 3.3-V Supply Operation · 2-mm x 2-mm Small-Outline No-Lead Package

2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS

文件：478.96 Kbytes Page：17 Pages

2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS

FEATURES · Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs · Clock Rates to 1 GHz – 250-ps Output Transition Times – 0.12 ps Typical Intrinsic Phase Jitter – Less than 630 ps Propagation Delay Times · 2.5-V or 3.3-V Supply Operation · 2-mm x 2-mm Small-Outline No-Lead Package

2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS

文件：497.5 Kbytes Page：17 Pages

2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS

文件：478.96 Kbytes Page：17 Pages