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SN54LS37价格
参考价格：￥49.9353
型号：SN54LS373J 品牌：Texas Instruments 备注：这里有SN54LS37多少钱，2025年最近7天走势，今日出价，今日竞价，SN54LS37批发/采购报价，SN54LS37行情走势销售排行榜，SN54LS37报价。| 型号 | 功能描述 | 生产厂家&企业 | LOGO | 操作 |
|---|---|---|---|---|
SN54LS37 | QUAD 2-INPUT NAND BUFFER
| Motorola 摩托罗拉 |   | |
SN54LS37 | QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS 文件：249.42 Kbytes Page：7 Pages | TI 德州仪器 | | |
OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 /74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (datachanges asynchronously) when Latch Enable (LE) | Motorola 摩托罗拉 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州仪器 | | ||
OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 /74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (datachanges asynchronously) when Latch Enable (LE) | Motorola 摩托罗拉 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI1 德州仪器 | | ||
OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 /74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (datachanges asynchronously) when Latch Enable (LE) | Motorola 摩托罗拉 | | ||
4-BIT D LATCH The SN54/74LS375 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input/output or indicator units. When the Enable (E) is HIGH, information present at the D input will be transferred to the Q output and, if E is HIGH, the Q output will follo | Motorola 摩托罗拉 | | ||
4-BIT D LATCH The SN54/74LS375 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input/output or indicator units. When the Enable (E) is HIGH, information present at the D input will be transferred to the Q output and, if E is HIGH, the Q output will follo | Motorola 摩托罗拉 | | ||
4.BIT BISTABLE LATCHES Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an | TI2 德州仪器 | | ||
4.BIT BISTABLE LATCHES Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an | TI2 德州仪器 | | ||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托罗拉 | | ||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托罗拉 | | ||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托罗拉 | | ||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托罗拉 | | ||
QUAD 2-INPUT NAND BUFFER
| Motorola 摩托罗拉 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：331.48 Kbytes Page：24 Pages | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：242.39 Kbytes Page：10 Pages | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：1.43118 Mbytes Page：30 Pages | TI1 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：694.69 Kbytes Page：28 Pages | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：1.43118 Mbytes Page：30 Pages | TI1 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：331.48 Kbytes Page：24 Pages | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：242.39 Kbytes Page：10 Pages | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：331.48 Kbytes Page：24 Pages | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：1.43118 Mbytes Page：30 Pages | TI1 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：694.69 Kbytes Page：28 Pages | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：1.43118 Mbytes Page：30 Pages | TI1 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：331.48 Kbytes Page：24 Pages | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：331.48 Kbytes Page：24 Pages | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：1.43118 Mbytes Page：30 Pages | TI1 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：242.39 Kbytes Page：10 Pages | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：694.69 Kbytes Page：28 Pages | TI 德州仪器 | | ||
8-Bit Registers with Three-State Outputs 文件：313.38 Kbytes Page：5 Pages | AMD 超威半导体 | | ||
8-Bit Registers with Three-State Outputs 文件：313.38 Kbytes Page：5 Pages | AMD 超威半导体 | | ||
8-Bit Registers with Three-State Outputs 文件：313.38 Kbytes Page：5 Pages | AMD 超威半导体 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：331.48 Kbytes Page：24 Pages | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：242.39 Kbytes Page：10 Pages | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：331.48 Kbytes Page：24 Pages | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：1.43118 Mbytes Page：30 Pages | TI1 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：694.69 Kbytes Page：28 Pages | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：1.43118 Mbytes Page：30 Pages | TI1 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：331.48 Kbytes Page：24 Pages | TI 德州仪器 | | ||
4-BIT BISTABLE LATCHES 文件：962.1 Kbytes Page：20 Pages | TI 德州仪器 | | ||
4-BIT BISTABLE LATCHES 文件：962.1 Kbytes Page：20 Pages | TI 德州仪器 | | ||
OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE 文件：180.21 Kbytes Page：16 Pages | TI 德州仪器 | | ||
OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE 文件：976.98 Kbytes Page：25 Pages | TI 德州仪器 | | ||
OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS 文件：1.4535 Mbytes Page：21 Pages | TI1 德州仪器 | | ||
OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE 文件：976.98 Kbytes Page：25 Pages | TI 德州仪器 | | ||
OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS 文件：1.4535 Mbytes Page：21 Pages | TI1 德州仪器 | | ||
OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE 文件：180.21 Kbytes Page：16 Pages | TI 德州仪器 | | ||
OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE 文件：180.21 Kbytes Page：16 Pages | TI 德州仪器 | | ||
OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE 文件：976.98 Kbytes Page：25 Pages | TI 德州仪器 | | ||
OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE 文件：976.98 Kbytes Page：25 Pages | TI 德州仪器 | | ||
OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS 文件：1.4535 Mbytes Page：21 Pages | TI1 德州仪器 | | ||
OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE 文件：180.21 Kbytes Page：16 Pages | TI 德州仪器 | | ||
OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE 文件：180.21 Kbytes Page：16 Pages | TI 德州仪器 | |
SN54LS37产品属性
- 类型
描述
- 型号
SN54LS37
- 制造商
Texas Instruments
- 功能描述
Latch Transparent 3-ST 8-CH D-Type 20-Pin CDIP Tube
- 制造商
Texas Instruments
- 功能描述
LATCH TRANSPARENT 3-ST 8CH D-TYPE 20CDIP - Rail/Tube
- 制造商
Texas Instruments
- 功能描述
OCTAL TRANSPARENT LATCH*NIC*
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI(德州仪器) |
2021+ |
8000 |
原装现货，欢迎询价 |
||||
TI(德州仪器) |
2405+ |
Original |
50000 |
只做原装优势现货库存,渠道可追溯 |
|||
TI/德州仪器 |
24+ |
CDIP |
22055 |
郑重承诺只做原装进口现货 |
|||
TI/德州仪器 |
24+ |
CDIP |
295 |
现货供应 |
|||
TI/德州仪器 |
2402+ |
CDIP-20 |
8324 |
原装正品!实单价优! |
|||
TI |
25+ |
CDIP (J) |
6000 |
原厂原装,价格优势 |
|||
TI |
23+ |
CDIP |
50000 |
全新原装正品现货,支持订货 |
|||
TI/德州仪器 |
23+ |
DIP |
90000 |
只做自库存深圳可交货 |
|||
TI |
2024+ |
N/A |
70000 |
柒号只做原装 现货价秒杀全网 |
|||
TI |
24+ |
DIP-16 |
3378 |
绝对原装公司现货供应!价格优势 |
SN54LS37规格书下载地址
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