QUAD 2-INPUT NAND BUFFER

军用 4 通道、2 输入、4.5V 至 5.5V 双极与非门

These devices contain four independent 2-input NAND buffer gates. The SN5437, SN54LS37 and SN54S37 are characterized for operation over the full military range of -55°C to 125°C. The SN7437, SN74LS37 and SN74S37 are characterized for operation from 0°C to 70°C.   • Package Options Include Plastic “Small Outline\" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs\n• Dependable Texas Instruments Quality and Reliability;

QUAD 2-INPUT NAND BUFFER

QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS

文件：249.42 Kbytes Page：7 Pages

丝印代码：SN54LS373J；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

丝印代码：SN54LS374J；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

丝印代码：SN54LS375J；4.BIT BISTABLE LATCHES

Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an

丝印代码：SN54LS375J；4.BIT BISTABLE LATCHES

Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT

OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 /74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (datachanges asynchronously) when Latch Enable (LE)

Octal transparent latch with 3-state outputs

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT

OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 /74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (datachanges asynchronously) when Latch Enable (LE)

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT

OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 /74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (datachanges asynchronously) when Latch Enable (LE)

4-BIT D LATCH

The SN54/74LS375 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input/output or indicator units. When the Enable (E) is HIGH, information present at the D input will be transferred to the Q output and, if E is HIGH, the Q output will follo

4.BIT BISTABLE LATCHES

Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an

4-BIT D LATCH

The SN54/74LS375 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input/output or indicator units. When the Enable (E) is HIGH, information present at the D input will be transferred to the Q output and, if E is HIGH, the Q output will follo

OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE

The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar

OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE

The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar

OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE

The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar

OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE

The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar

QUAD 2-INPUT NAND BUFFER

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：1.43118 Mbytes Page：30 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：331.48 Kbytes Page：24 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：242.39 Kbytes Page：10 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：694.69 Kbytes Page：28 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：1.43118 Mbytes Page：30 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：331.48 Kbytes Page：24 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：331.48 Kbytes Page：24 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：242.39 Kbytes Page：10 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：694.69 Kbytes Page：28 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：1.43118 Mbytes Page：30 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：1.43118 Mbytes Page：30 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：331.48 Kbytes Page：24 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：331.48 Kbytes Page：24 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：694.69 Kbytes Page：28 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：1.43118 Mbytes Page：30 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：242.39 Kbytes Page：10 Pages

8-Bit Registers with Three-State Outputs

文件：313.38 Kbytes Page：5 Pages

8-Bit Registers with Three-State Outputs

文件：313.38 Kbytes Page：5 Pages

8-Bit Registers with Three-State Outputs

文件：313.38 Kbytes Page：5 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：331.48 Kbytes Page：24 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：331.48 Kbytes Page：24 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：694.69 Kbytes Page：28 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：242.39 Kbytes Page：10 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：1.43118 Mbytes Page：30 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：1.43118 Mbytes Page：30 Pages

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：331.48 Kbytes Page：24 Pages

4-BIT BISTABLE LATCHES

文件：962.1 Kbytes Page：20 Pages

4-BIT BISTABLE LATCHES

文件：962.1 Kbytes Page：20 Pages

OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE

文件：976.98 Kbytes Page：25 Pages

OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE

文件：180.21 Kbytes Page：16 Pages

OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS

文件：1.4535 Mbytes Page：21 Pages

OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE

文件：976.98 Kbytes Page：25 Pages

OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS

文件：1.4535 Mbytes Page：21 Pages

OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE

文件：180.21 Kbytes Page：16 Pages

OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE

文件：180.21 Kbytes Page：16 Pages

OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE

文件：976.98 Kbytes Page：25 Pages