4-BIT PARALLEL-ACCESS SHIFT REGISTERS

1FEATURES · Synchronous Parallel Load · Positive-Edge-Triggered Clocking · J and K Inputs to First Stage · Complementary Outputs From Last Stage · Package Options: Plastic and Ceramic DIPS and Ceramic Chip Carriers · Dependable Texas lnstruments Quality and Reliability DESCRIPTION/ORDER

4-BIT PARALLEL-ACCESS SHIFT REGISTERS

文件：232.86 Kbytes Page：10 Pages

4-BIT PARALLEL-ACCESS SHIFT REGISTERS

1FEATURES · Synchronous Parallel Load · Positive-Edge-Triggered Clocking · J and K Inputs to First Stage · Complementary Outputs From Last Stage · Package Options: Plastic and Ceramic DIPS and Ceramic Chip Carriers · Dependable Texas lnstruments Quality and Reliability DESCRIPTION/ORDER

High-Speed CMOS Logic 4-Bit Parallel Access Register

Features • Asynchronous Master Reset • J, K, (D) Inputs to First Stage • Fully Synchronous Serial or Parallel Data Transfer • Shift Right and Parallel Load Capability • Complementary Output From Last Stage • Buffered Inputs • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout

8 BIT PIPO SHIFT REGISTER

DESCRIPTION The M54/74HC195 is a high speed CMOS 4 BIT PIPO SHIFT REGISTER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED tPD = 13 ns (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA

High-Speed CMOS Logic 4-Bit Parallel Access Register

文件：335.19 Kbytes Page：11 Pages

High-Speed CMOS Logic 4-Bit Parallel Access Register

文件：632.02 Kbytes Page：16 Pages

4-Bit Parallel Shift Register

文件：171.07 Kbytes Page：6 Pages