DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：445.61 Kbytes Page：14 Pages

High Speed CMOS Logic

Features: Output Drive Capability: 10 LSTTL Loads Bus Drive Capability: 15 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 54LS112 Full Military Temperature Range.

High Speed CMOS Logic

文件：683.61 Kbytes Page：6 Pages

High Speed CMOS Logic

文件：440.21 Kbytes Page：6 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：346.89 Kbytes Page：13 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：643.79 Kbytes Page：18 Pages