DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

Controlled Baseline − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† 4.5-V to 5.5-V VCC Operation Inputs Accept Voltages

SN74ACT74-Q1 Automotive Dual D-Type Flip-Flops With Preset and Clear

1 Features • AEC-Q100 qualified for automotive applications: – Device temperature grade 1: -40°C to +125°C – Device HBM ESD classification level 2 – Device CDM ESD classification level C4B • Available in wettable flank QFN package • Operating voltage range of 4.5V to 5.5V • TTL-compatible i

SNx4ACT74 Dual Positive-Edge-Triggered D-Type Flip-Flops

1 Features • 4.5V to 5.5V VCC operation • Inputs accept voltages to 5.5V • Max tpd of 10.5ns at 5V • Inputs are TTL-voltage compatible 2 Description The 'ACT74 dual positive-edge-triggered devices are D-type flip-flops.

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：86.43 Kbytes Page：6 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：528.92 Kbytes Page：16 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：1.15348 Mbytes Page：21 Pages

具有清零和预置端的双路正边沿触发式 D 型触发器

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：528.92 Kbytes Page：16 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：86.43 Kbytes Page：6 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：86.43 Kbytes Page：6 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：86.43 Kbytes Page：6 Pages

Advanced CMOS TTL Input

Features: Inputs directly accept TTL Outputs Directly Interface to CMOS, NMOS, and TTL Outputs Source/Sink 24 mA Asynchronous Set-Reset Capability Lower power alternative to bipolar logic Functionally compatible with bipolar 54LS74 Direct drop-in replacement for obsolete components in long

Dual D-Type Positive Edge-Triggered Flip-Flop

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Advanced CMOS TTL Input

文件：504.1 Kbytes Page：6 Pages

Advanced CMOS TTL Input

文件：505.14 Kbytes Page：6 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：325.79 Kbytes Page：10 Pages