DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

Qualified for Automotive Applications Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current − Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design desc

具有设置和复位端的双路正边沿触发式 D 型触发器

The ’ACT74 dual positive-edge-triggered devices are D-type flip-flops.\n\n A low level at the preset (PRE)\\ or clear (CLR)\\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\\ and CLR\\ are inactive (high), data at the data (D) input meeting the setup time r • Inputs Are TTL-Voltage Compatible\n• Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption\n• Balanced Propagation Delays\n• ±24-mA Output Drive Current \n• Fanout to 15 F Devices\n \n• SCR-Latchup-Resistant CMOS Process and Circuit Design\n• Exceeds 2-kV ESD Protection Per M;

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

文件：887.59 Kbytes Page：14 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：325.79 Kbytes Page：10 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

文件：887.59 Kbytes Page：14 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

文件：887.59 Kbytes Page：14 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：325.79 Kbytes Page：10 Pages

Dual D-Type Positive Edge-Triggered Flip-Flop

文件：180.3 Kbytes Page：8 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：86.43 Kbytes Page：6 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：86.43 Kbytes Page：6 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：86.43 Kbytes Page：6 Pages