Dual Monostable Multivibrator

Dual Monostable Multivibrator The SL74HC221 is identical in pinout to the LS/ALS221. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 3.0

Dual monostable multivibrator

Dual non-retriggerable monostable multivibrator with reset

The 74HC/HCT221 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT221 are dual non-retriggerable monostable multivibrators. Each multivibrator features an active LOW-goin

Dual non-retriggerable monostable multivibrator with reset

The 74HC/HCT221 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT221 are dual non-retriggerable monostable multivibrators. Each multivibrator features an active LOW-goin

Dual non-retriggerable monostable multivibrator with reset

The 74HC/HCT221 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT221 are dual non-retriggerable monostable multivibrators. Each multivibrator features an active LOW-goin

DUAL MONOSTABLE MULTIVIBRATOR

DESCRIPTION The M54/74HC221/221A are high speed CMOS MONOSTABLE multivibrators fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. There are two trigger inputs, AINPUT (negative edge) and

DUAL MONOSTABLE MULTIVIBRATOR

DESCRIPTION The M54/74HC221/221A are high speed CMOS MONOSTABLE multivibrators fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. There are two trigger inputs, AINPUT (negative edge) and