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SL4价格
参考价格:¥36.1179
型号:SL402FX 品牌:Switchcraft 备注:这里有SL4多少钱,2025年最近7天走势,今日出价,今日竞价,SL4批发/采购报价,SL4行情走势销售排行榜,SL4报价。型号 | 功能描述 | 生产厂家&企业 | LOGO | 操作 |
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SL4 | SL4 Series Single-In-Line Passive Single Output 50 W Impedance Delays 文件:19.45 Kbytes Page:1 Pages | RHOMBUS-IND | ||
SL4 | Circuit Protection Solutions Low Voltage Fuse Links Catalogue 文件:4.91849 Mbytes Page:55 Pages | COOPER COOPER | ||
Quad 2-Input NOR Gate The SL4001B NOR gates provide the system designer with direct emplementation of the NOR function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 mA at 18 V over full package temperature range; 100 nA at 18 V and 25°C • Noise margin (over full package temperature range) | SLS System Logic Semiconductor | |||
Quad 2-Input NOR Gate The SL4001B NOR gates provide the system designer with direct emplementation of the NOR function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 mA at 18 V over full package temperature range; 100 nA at 18 V and 25°C • Noise margin (over full package temperature range) | SLS System Logic Semiconductor | |||
Quad 2-Input NOR Gate The SL4001B NOR gates provide the system designer with direct emplementation of the NOR function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 mA at 18 V over full package temperature range; 100 nA at 18 V and 25°C • Noise margin (over full package temperature range) | SLS System Logic Semiconductor | |||
1 AMP SMD SILICON RECTIFIER 1 AMP SMD SILICON RECTIFIER | Surge | |||
Dual 4-Input NOR Gate Dual 4-Input NOR Gate High-Voltage Silicon-Gate CMOS The SL4002B NOR gates provide the system designer with direct emplementation of the NOR function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25°C • N | SLS System Logic Semiconductor | |||
Dual 4-Input NOR Gate Dual 4-Input NOR Gate High-Voltage Silicon-Gate CMOS The SL4002B NOR gates provide the system designer with direct emplementation of the NOR function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25°C • N | SLS System Logic Semiconductor | |||
Dual 4-Input NOR Gate Dual 4-Input NOR Gate High-Voltage Silicon-Gate CMOS The SL4002B NOR gates provide the system designer with direct emplementation of the NOR function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25°C • N | SLS System Logic Semiconductor | |||
1 AMP SMD SILICON RECTIFIER 1 AMP SMD SILICON RECTIFIER | Surge | |||
1 AMP SMD SILICON RECTIFIER 1 AMP SMD SILICON RECTIFIER | Surge | |||
1 AMP SMD SILICON RECTIFIER 1 AMP SMD SILICON RECTIFIER | Surge | |||
1 AMP SMD SILICON RECTIFIER 1 AMP SMD SILICON RECTIFIER | Surge | |||
1 AMP SMD SILICON RECTIFIER 1 AMP SMD SILICON RECTIFIER | Surge | |||
1 AMP SMD SILICON RECTIFIER 1 AMP SMD SILICON RECTIFIER | Surge | |||
Quad 2-Input NAND Gate Quad 2-Input NAND Gate High-Voltage Silicon-Gate CMOS The SL4011B NAND gates provide the system designer with direct emplementation of the NAND function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25°C | SLS System Logic Semiconductor | |||
Quad 2-Input NAND Gate Quad 2-Input NAND Gate High-Voltage Silicon-Gate CMOS The SL4011B NAND gates provide the system designer with direct emplementation of the NAND function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25°C | SLS System Logic Semiconductor | |||
Quad 2-Input NAND Gate Quad 2-Input NAND Gate High-Voltage Silicon-Gate CMOS The SL4011B NAND gates provide the system designer with direct emplementation of the NAND function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25°C | SLS System Logic Semiconductor | |||
Dual 4-Input NAND Gate Dual 4-Input NAND Gate High-Voltage Silicon-Gate CMOS The SL4012B NAND gates provide the system designer with direct emplementation of the NAND function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25° | SLS System Logic Semiconductor | |||
Dual 4-Input NAND Gate Dual 4-Input NAND Gate High-Voltage Silicon-Gate CMOS The SL4012B NAND gates provide the system designer with direct emplementation of the NAND function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25° | SLS System Logic Semiconductor | |||
Dual 4-Input NAND Gate Dual 4-Input NAND Gate High-Voltage Silicon-Gate CMOS The SL4012B NAND gates provide the system designer with direct emplementation of the NAND function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25° | SLS System Logic Semiconductor | |||
Dual D Flip-Flop Dual D Flip-Flop High-Voltage Silicon-Gate CMOS The SL4013B consists of two identical, independent data-type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Q output t | SLS System Logic Semiconductor | |||
Dual D Flip-Flop Dual D Flip-Flop High-Voltage Silicon-Gate CMOS The SL4013B consists of two identical, independent data-type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Q output t | SLS System Logic Semiconductor | |||
Dual D Flip-Flop Dual D Flip-Flop High-Voltage Silicon-Gate CMOS The SL4013B consists of two identical, independent data-type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Q output t | SLS System Logic Semiconductor | |||
Dual 4-Stage Static Shift Register Dual 4-Stage Static Shift Register High-Voltage Silicon-Gate CMOS The SL4015B consists of two identical, independent, 4-stage serial input/parallel-output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. “Q” outputs are available from e | SLS System Logic Semiconductor | |||
Dual 4-Stage Static Shift Register Dual 4-Stage Static Shift Register High-Voltage Silicon-Gate CMOS The SL4015B consists of two identical, independent, 4-stage serial input/parallel-output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. “Q” outputs are available from e | SLS System Logic Semiconductor | |||
Dual 4-Stage Static Shift Register Dual 4-Stage Static Shift Register High-Voltage Silicon-Gate CMOS The SL4015B consists of two identical, independent, 4-stage serial input/parallel-output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. “Q” outputs are available from e | SLS System Logic Semiconductor | |||
Counter/Divider Counter/Divider High-Voltage Silicon-Gate CMOS The SL4017B is 5-stage Johnson counter having 10 decoded outputs. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise an | SLS System Logic Semiconductor | |||
Counter/Divider Counter/Divider High-Voltage Silicon-Gate CMOS The SL4017B is 5-stage Johnson counter having 10 decoded outputs. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise an | SLS System Logic Semiconductor | |||
Counter/Divider Counter/Divider High-Voltage Silicon-Gate CMOS The SL4017B is 5-stage Johnson counter having 10 decoded outputs. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise an | SLS System Logic Semiconductor | |||
Quad AND/OR Select Gate Quad AND/OR Select Gate High-Voltage Silicon-Gate CMOS The SL4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single 2-input gate. Selection is accomplished by control bits Sa and Sb .In addition to selection of either channel A or | SLS System Logic Semiconductor | |||
Quad AND/OR Select Gate Quad AND/OR Select Gate High-Voltage Silicon-Gate CMOS The SL4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single 2-input gate. Selection is accomplished by control bits Sa and Sb .In addition to selection of either channel A or | SLS System Logic Semiconductor | |||
Quad AND/OR Select Gate Quad AND/OR Select Gate High-Voltage Silicon-Gate CMOS The SL4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single 2-input gate. Selection is accomplished by control bits Sa and Sb .In addition to selection of either channel A or | SLS System Logic Semiconductor | |||
14 Stage Ripple-Carry Binary Counter/Divider The SL4020B is ripple-carry binary counter. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse | SLS System Logic Semiconductor | |||
14 Stage Ripple-Carry Binary Counter/Divider The SL4020B is ripple-carry binary counter. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse | SLS System Logic Semiconductor | |||
14 Stage Ripple-Carry Binary Counter/Divider The SL4020B is ripple-carry binary counter. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse | SLS System Logic Semiconductor | |||
Triple 3-Input NAND Gate Triple 3-Input NAND Gate High-Voltage Silicon-Gate CMOS The SL4023B NAND gates provide the system designer with direct emplementation of the NAND function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 2 | SLS System Logic Semiconductor | |||
Triple 3-Input NAND Gate Triple 3-Input NAND Gate High-Voltage Silicon-Gate CMOS The SL4023B NAND gates provide the system designer with direct emplementation of the NAND function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 2 | SLS System Logic Semiconductor | |||
Triple 3-Input NAND Gate Triple 3-Input NAND Gate High-Voltage Silicon-Gate CMOS The SL4023B NAND gates provide the system designer with direct emplementation of the NAND function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 2 | SLS System Logic Semiconductor | |||
Triple 3-Input NOR Gate Triple 3-Input NOR Gate High-Voltage Silicon-Gate CMOS The SL4025B NOR gates provide the system designer with direct emplementation of the NOR function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25° | SLS System Logic Semiconductor | |||
Triple 3-Input NOR Gate Triple 3-Input NOR Gate High-Voltage Silicon-Gate CMOS The SL4025B NOR gates provide the system designer with direct emplementation of the NOR function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25° | SLS System Logic Semiconductor | |||
Triple 3-Input NOR Gate Triple 3-Input NOR Gate High-Voltage Silicon-Gate CMOS The SL4025B NOR gates provide the system designer with direct emplementation of the NOR function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25° | SLS System Logic Semiconductor | |||
BCD-to-Decimal Decoder BCD-to-Decimal Decoder High-Voltage Silicon-Gate CMOS The SL4028B types are BCD-to-decimal or binary-to-octal decoders consisting of buffering on all 4 inputs, decoding-logic gates, and 10 output buffers. A BCD code applied to the four inputs, A0 to A3 results in a high level at the selected one | SLS System Logic Semiconductor | |||
BCD-to-Decimal Decoder BCD-to-Decimal Decoder High-Voltage Silicon-Gate CMOS The SL4028B types are BCD-to-decimal or binary-to-octal decoders consisting of buffering on all 4 inputs, decoding-logic gates, and 10 output buffers. A BCD code applied to the four inputs, A0 to A3 results in a high level at the selected one | SLS System Logic Semiconductor | |||
BCD-to-Decimal Decoder BCD-to-Decimal Decoder High-Voltage Silicon-Gate CMOS The SL4028B types are BCD-to-decimal or binary-to-octal decoders consisting of buffering on all 4 inputs, decoding-logic gates, and 10 output buffers. A BCD code applied to the four inputs, A0 to A3 results in a high level at the selected one | SLS System Logic Semiconductor | |||
Presettable Up/Down Counter Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS The SL4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consists of a single CLOCK, CARRY IN,(CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, | SLS System Logic Semiconductor | |||
Presettable Up/Down Counter Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS The SL4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consists of a single CLOCK, CARRY IN,(CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, | SLS System Logic Semiconductor | |||
Presettable Up/Down Counter Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS The SL4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consists of a single CLOCK, CARRY IN,(CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, | SLS System Logic Semiconductor | |||
Quad Exclusive-OR Gate The SL4030B types consist of four independent Exclusive-OR gates. The SL4030B provides the system designer with a means for direct implementation of the Exlusive-OR function. · Operating Voltage Range: 3.0 to 18 V · Maximum input current of 1 μA at 18 V over full package temperature range; | SLS System Logic Semiconductor | |||
Single-Input Voltage, Synchronous Buck Regulator DESCRIPTION The IR3846 SupIRBuck® is an easy-to-use, fully integrated and highly efficient DC/DC regulator. The onboard PWM controller and MOSFETs make IR3846 a space-efficient solution, providing accurate power delivery for low output voltage and high current applications. IR3846 is a versa | IRF | |||
Quad Exclusive-OR Gate The SL4030B types consist of four independent Exclusive-OR gates. The SL4030B provides the system designer with a means for direct implementation of the Exlusive-OR function. · Operating Voltage Range: 3.0 to 18 V · Maximum input current of 1 μA at 18 V over full package temperature range; | SLS System Logic Semiconductor | |||
Quad Exclusive-OR Gate The SL4030B types consist of four independent Exclusive-OR gates. The SL4030B provides the system designer with a means for direct implementation of the Exlusive-OR function. · Operating Voltage Range: 3.0 to 18 V · Maximum input current of 1 μA at 18 V over full package temperature range; | SLS System Logic Semiconductor | |||
Quad Exclusive-OR Gate The SL4030B types consist of four independent Exclusive-OR gates. The SL4030B provides the system designer with a means for direct implementation of the Exlusive-OR function. · Operating Voltage Range: 3.0 to 18 V · Maximum input current of 1 μA at 18 V over full package temperature range; | SLS System Logic Semiconductor | |||
8-Stage Static Bidirectional Parallel/ Serial Input/Output Bus Register 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register High-Voltage Silicon-Gate CMOS The SL4034B is a static eight-stage parallel-or serial-input paralleloutput register. It can be used to: 1) bidirectionally transfer parallel information between two buses, 2) convert serial dat | SLS System Logic Semiconductor | |||
8-Stage Static Bidirectional Parallel/ Serial Input/Output Bus Register 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register High-Voltage Silicon-Gate CMOS The SL4034B is a static eight-stage parallel-or serial-input paralleloutput register. It can be used to: 1) bidirectionally transfer parallel information between two buses, 2) convert serial dat | SLS System Logic Semiconductor | |||
Quad 3-State R/S Latch Quad 3-State R/S Latch High-Voltage Silicon-Gate CMOS The SL4043B types are quad cross-coupled 3-state CMOS NOR latces. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic “1” or high on the ENABLE input connects t | SLS System Logic Semiconductor | |||
Quad 3-State R/S Latch Quad 3-State R/S Latch High-Voltage Silicon-Gate CMOS The SL4043B types are quad cross-coupled 3-state CMOS NOR latces. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic “1” or high on the ENABLE input connects t | SLS System Logic Semiconductor | |||
Quad 3-State R/S Latch Quad 3-State R/S Latch High-Voltage Silicon-Gate CMOS The SL4043B types are quad cross-coupled 3-state CMOS NOR latces. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic “1” or high on the ENABLE input connects t | SLS System Logic Semiconductor | |||
Hex Buffer/Converter The SL4049B is inverting hex buffers and feature logic-level conversion using only one supply (voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logic-level conversions. These devices are intended for use as CMOS to DTL/TTL converter | SLS System Logic Semiconductor | |||
Hex Buffer/Converter The SL4049B is inverting hex buffers and feature logic-level conversion using only one supply (voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logic-level conversions. These devices are intended for use as CMOS to DTL/TTL converter | SLS System Logic Semiconductor |
SL4产品属性
- 类型
描述
- 型号
SL4
- 制造商
RHOMBUS-IND
- 制造商全称
Rhombus Industries Inc.
- 功能描述
SL4 Series Single-In-Line Passive Single Output 50 W Impedance Delays
IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
Vishay(威世) |
24+ |
标准封装 |
7263 |
原厂直销,大量现货库存,交期快。价格优,支持账期 |
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Slkor(萨科微) |
24+ |
SOT23(TO236) |
50000 |
现货供应,当天可交货!免费送样,原厂技术支持!!! |
|||
AUK |
2016+ |
SOT23 |
4735 |
只做原装,假一罚十,公司可开17%增值税发票! |
|||
PLESSEY |
23+ |
DIP |
20000 |
全新原装假一赔十 |
|||
VISHAY/威世 |
23+ |
DO-214AB(SMC) |
12700 |
买原装认准中赛美 |
|||
VISHAY SEMICONDUCTOR |
25+ |
SMD |
918000 |
明嘉莱只做原装正品现货 |
|||
AUK |
25+ |
TO92 |
54648 |
百分百原装现货 实单必成 欢迎询价 |
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VISHAY/威世 |
22+ |
100000 |
代理渠道/只做原装/可含税 |
||||
FLOETH |
25+ |
全新-电源模块 |
10238 |
FLOETH电源模块SL4UM-1503.3交期短价格好#即刻询购立享优惠#长期有排单订 |
|||
24+ |
DO-214AB |
20000 |
全新原厂原装,进口正品现货,正规渠道可含税!! |
SL4芯片相关品牌
SL4规格书下载地址
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SL4数据表相关新闻
SL820原装现货,价格低
SL820原装现货,价格低
2024-9-9SL44-E3/57T
进口代理
2023-9-22SL3281EFHZ-T
SL3281EFHZ-T
2022-7-8SL353LT HONEYWELL深圳市光华微科技有限公司0755-83203002
原装正品,假一赔十
2020-6-5SL3.50/03/90G3.2SNORBX原装魏德米勒端子,深圳现货
只做原装,假一罚十,可开16%增值税票。主营:魏德米勒,TE.NXP.ON.Renesas.Microchip.英飞凌.ALLEGRO
2019-4-1SL431AM-可编程电压基准
特点 •可编程输出电压为36伏特 •灌电流能力的一点○毫安至100mA •典型的低动态阻抗0.15Ω •温度补偿操作的全额定工作温度 •相当于全范围温度为50ppm/ ° C(典型值)系数 •低输出噪声电压 •电压参考公差:±1.0%(打= 25℃) 应用 办公室 通信设备 测量设备 国内电气化等
2013-3-15
DdatasheetPDF页码索引
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