19-OUTPUT PCIE GEN 3 BUFFER

Features  Nineteen 0.7 V low-power, pushpull HCSL PCIe Gen 3 outputs  100 MHz /133 MHz PLL operation, supports PCIe and QPI  PLL bandwidth SW SMBUS programming overrides the latch value from HW pin  9 selectable SMBUS addresses  SMBus address configurable to allow multiple buffers

PLL or bypass mode

文件：1.4135 Mbytes Page：34 Pages

19-OUTPUT PCIE GEN 3 BUFFER

Features  Nineteen 0.7 V low-power, pushpull HCSL PCIe Gen 3 outputs  100 MHz /133 MHz PLL operation, supports PCIe and QPI  PLL bandwidth SW SMBUS programming overrides the latch value from HW pin  9 selectable SMBUS addresses  SMBus address configurable to allow multiple buffers

19-OUTPUT PCIE GEN 3 BUFFER

Features  Nineteen 0.7 V low-power, pushpull HCSL PCIe Gen 3 outputs  100 MHz /133 MHz PLL operation, supports PCIe and QPI  PLL bandwidth SW SMBUS programming overrides the latch value from HW pin  9 selectable SMBUS addresses  SMBus address configurable to allow multiple buffers

PLL or bypass mode

文件：1.4135 Mbytes Page：34 Pages

封装/外壳：72-VFQFN 裸露焊盘 包装：管件 描述：1:19 LOW-POWER PCIE FANOUT/ZERO- 集成电路（IC） 应用特定时钟/定时

封装/外壳：72-VFQFN 裸露焊盘 包装：卷带（TR） 描述：1:19 LOW-POWER PCIE FANOUT/ZERO- 集成电路（IC） 应用特定时钟/定时

PLL or bypass mode

文件：1.4135 Mbytes Page：34 Pages