外置高压MOS管的原边控制开关电源

65 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

65 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

67 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

67 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

67 MSPS Digital Receive Signal Processor

文件：399.31 Kbytes Page：44 Pages