型号 功能描述 生产厂家 企业 LOGO 操作
AD6620S/PCB

65 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

AD

亚德诺

AD6620S/PCB

67 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

AD

亚德诺

AD6620S/PCB

67 MSPS Digital Receive Signal Processor

文件:399.31 Kbytes Page:44 Pages

AD

亚德诺

65 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

AD

亚德诺

67 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

AD

亚德诺

65 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

AD

亚德诺

67 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

AD

亚德诺

67 MSPS Digital Receive Signal Processor

文件:399.31 Kbytes Page:44 Pages

AD

亚德诺

AD6620S/PCB产品属性

  • 类型

    描述

  • 型号

    AD6620S/PCB

  • 制造商

    Analog Devices

  • 功能描述

    DUAL CHANNEL DECIMATING RECEIV

  • 制造商

    Analog Devices

  • 功能描述

    SGNL PROCESSOR 169CSPBGA - Bulk

更新时间:2025-9-25 22:50:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
恩XP
23+
NA
2500
全新原装假一赔十
ADI/亚德诺
20+
QFP
35830
原装优势主营型号-可开原型号增税票
ADI
23+
BGAQFP
8659
原装公司现货!原装正品价格优势.
ADI/亚德诺
24+
289
现货供应
AD
23+
QFP
3600
绝对全新原装!现货!特价!请放心订购!
AD
2138+
QFP
8960
专营BGA,QFP原装现货,假一赔十
ADI/亚德诺
23+
BGA
5000
原厂授权代理,海外优势订货渠道。可提供大量库存,详
ADI(亚德诺)
23+
NA
20094
正纳10年以上分销经验原装进口正品做服务做口碑有支持
ADI
409
QFP
325
原装正品
ADI
24+
原厂原装
527
原装房间现货!

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