3A Step-Down Switching Regulator with Adjustable Switching Frequency

Description The SC4520 is a current mode switching regulator with an integrated switch and an adjustable frequency with enable function. The integrated switch allows for cost effective, low power solutions with a peak switch current of 3 amps. An adjustable high frequency of 100kHz to 600kHz prov

封装/外壳：8-SOIC（0.154"，3.90mm 宽）裸露焊盘 功能：降压 包装：管件 描述：IC REG BUCK ADJUSTABLE 3A 8SOIC 集成电路（IC） 稳压器 - DC-DC 开关稳压器

封装/外壳：8-SOIC（0.154"，3.90mm 宽）裸露焊盘 功能：降压 包装：卷带（TR） 描述：IC REG BUCK ADJUSTABLE 3A 8SOIC 集成电路（IC） DC DC 开关稳压器

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou