Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

Dual binary counter

1. General description The HEF4520B is a dual 4-bit internally synchronous binary counter with two clock inputs (nCP0 and nCP1), buffered outputs from all four bit positions (nQ0 to nQ3) and an asynchronous master reset input (nMR). The counter advances on either the LOW-to-HIGH transition of n

Tolerant of slow clock rise and fall times

Dual binary counter

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC BINARY COUNTER DUAL 16SOIC 集成电路（IC） 计数器，除法器

Tolerant of slow clock rise and fall times

Dual binary counter

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC BINARY COUNTER DUAL 16SOIC 集成电路（IC） 计数器，除法器

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou

Dual binary counter

DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR). The cou