位置：首页 > IC中文资料第3735页 > S70K
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
S70K | Silicon Standard Recovery Diode 文件：461.46 Kbytes Page：2 Pages | ETCList of Unclassifed Manufacturers 未分类制造商 |   | |
S70K | Silicon Standard Recovery Diode 文件：646.62 Kbytes Page：3 Pages | GENESIC | | |
S70K | Silicon Standard Recovery Diode 文件：631.22 Kbytes Page：3 Pages | GENESIC | | |
S70K | Silicon Standard Recovery Diode 文件：805.37 Kbytes Page：3 Pages | GENESIC | | |
S70K | 封装/外壳：DO-203AB，DO-5，接线柱 包装：散装 描述：DIODE GEN PURP 800V 70A DO5 分立半导体产品 二极管 - 整流器 - 单 | GENESIC | | |
S70K | Standard Recovery Rectifiers | Navitas 纳微半导体 | | |
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) HYPERBUS™ interface, 1.8 V/3.0 V Features • Interface - HYPERBUS™ interface - 1.8 V / 3.0 V interface support • Single-ended clock (CK) - 11 bus signals • Optional differential clock (CK, CK#) - 12 bus signals - Chip select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional read-write data strobe | Infineon 英飞凌 | | ||
HyperRAM (Self-Refresh DRAM) 3.0 V/1.8 V, 128-Mbit, Automotive-E (Grade 1) Features Interface • HyperBus Interface • 1.8 V / 3.0 V interface support - Single-ended clock (CK) - 11 bus signals - Optional differential clock (CK, CK#) - 12 bus signals • Chip Select (CS#) • 8-bit data bus (DQ[7:0]) • Hardware reset (RESET#) • Bidirectional Read-Write Data Strobe (RW | Infineon 英飞凌 | | ||
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) HYPERBUS™ interface, 1.8 V/3.0 V Features • Interface - HYPERBUS™ interface - 1.8 V / 3.0 V interface support • Single-ended clock (CK) - 11 bus signals • Optional differential clock (CK, CK#) - 12 bus signals - Chip select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional read-write data strobe | Infineon 英飞凌 | | ||
HyperRAM (Self-Refresh DRAM) 3.0 V/1.8 V, 128-Mbit, Automotive-E (Grade 1) Features Interface • HyperBus Interface • 1.8 V / 3.0 V interface support - Single-ended clock (CK) - 11 bus signals - Optional differential clock (CK, CK#) - 12 bus signals • Chip Select (CS#) • 8-bit data bus (DQ[7:0]) • Hardware reset (RESET#) • Bidirectional Read-Write Data Strobe (RW | Infineon 英飞凌 | | ||
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) HYPERBUS™ interface, 1.8 V/3.0 V Features • Interface - HYPERBUS™ interface - 1.8 V / 3.0 V interface support • Single-ended clock (CK) - 11 bus signals • Optional differential clock (CK, CK#) - 12 bus signals - Chip select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional read-write data strobe | Infineon 英飞凌 | | ||
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) HYPERBUS™ interface, 1.8 V/3.0 V Features • Interface - HYPERBUS™ interface - 1.8 V / 3.0 V interface support • Single-ended clock (CK) - 11 bus signals • Optional differential clock (CK, CK#) - 12 bus signals - Chip select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional read-write data strobe | Infineon 英飞凌 | | ||
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) HYPERBUS™ interface, 1.8 V/3.0 V Features • Interface - HYPERBUS™ interface - 1.8 V / 3.0 V interface support • Single-ended clock (CK) - 11 bus signals • Optional differential clock (CK, CK#) - 12 bus signals - Chip select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional read-write data strobe | Infineon 英飞凌 | | ||
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) HYPERBUS™ interface, 1.8 V/3.0 V Features • Interface - HYPERBUS™ interface - 1.8 V / 3.0 V interface support • Single-ended clock (CK) - 11 bus signals • Optional differential clock (CK, CK#) - 12 bus signals - Chip select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional read-write data strobe | Infineon 英飞凌 | | ||
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) HYPERBUS™ interface, 1.8 V/3.0 V Features • Interface - HYPERBUS™ interface - 1.8 V / 3.0 V interface support • Single-ended clock (CK) - 11 bus signals • Optional differential clock (CK, CK#) - 12 bus signals - Chip select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional read-write data strobe | Infineon 英飞凌 | | ||
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) HYPERBUS™ interface, 1.8 V/3.0 V Features • Interface - HYPERBUS™ interface - 1.8 V / 3.0 V interface support • Single-ended clock (CK) - 11 bus signals • Optional differential clock (CK, CK#) - 12 bus signals - Chip select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional read-write data strobe | Infineon 英飞凌 | | ||
HyperRAM (Self-Refresh DRAM) 3.0 V/1.8 V, 128-Mbit, Automotive-E (Grade 1) Features Interface • HyperBus Interface • 1.8 V / 3.0 V interface support - Single-ended clock (CK) - 11 bus signals - Optional differential clock (CK, CK#) - 12 bus signals • Chip Select (CS#) • 8-bit data bus (DQ[7:0]) • Hardware reset (RESET#) • Bidirectional Read-Write Data Strobe (RW | Infineon 英飞凌 | | ||
HyperRAM (Self-Refresh DRAM) 3.0 V/1.8 V, 128-Mbit, Automotive-E (Grade 1) Features Interface • HyperBus Interface • 1.8 V / 3.0 V interface support - Single-ended clock (CK) - 11 bus signals - Optional differential clock (CK, CK#) - 12 bus signals • Chip Select (CS#) • 8-bit data bus (DQ[7:0]) • Hardware reset (RESET#) • Bidirectional Read-Write Data Strobe (RW | Infineon 英飞凌 | | ||
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) HYPERBUS™ interface, 1.8 V/3.0 V Features • Interface - HYPERBUS™ interface - 1.8 V / 3.0 V interface support • Single-ended clock (CK) - 11 bus signals • Optional differential clock (CK, CK#) - 12 bus signals - Chip select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional read-write data strobe | Infineon 英飞凌 | | ||
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) HYPERBUS™ interface, 1.8 V/3.0 V Features • Interface - HYPERBUS™ interface - 1.8 V / 3.0 V interface support • Single-ended clock (CK) - 11 bus signals • Optional differential clock (CK, CK#) - 12 bus signals - Chip select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional read-write data strobe | Infineon 英飞凌 | | ||
128 Mb HYPERRAM™ self-refresh DRAM Features • Interface - xSPI (Octal) interface - 1.8 V / 3.0 V interface support • Single ended clock (CK) - 11 bus signals • Optional differential clock (CK, CK#) - 12 bus signals - Chip Select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional read-write data stro | Infineon 英飞凌 | | ||
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) HYPERBUS™ interface, 1.8 V/3.0 V Features • Interface - HYPERBUS™ interface - 1.8 V / 3.0 V interface support • Single-ended clock (CK) - 11 bus signals • Optional differential clock (CK, CK#) - 12 bus signals - Chip select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional read-write data strobe | Infineon 英飞凌 | | ||
HyperRAM (Self-Refresh DRAM) 3.0 V/1.8 V, 128-Mbit, Automotive-E (Grade 1) Features Interface • HyperBus Interface • 1.8 V / 3.0 V interface support - Single-ended clock (CK) - 11 bus signals - Optional differential clock (CK, CK#) - 12 bus signals • Chip Select (CS#) • 8-bit data bus (DQ[7:0]) • Hardware reset (RESET#) • Bidirectional Read-Write Data Strobe (RW | Infineon 英飞凌 | | ||
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) HYPERBUS™ interface, 1.8 V/3.0 V Features • Interface - HYPERBUS™ interface - 1.8 V / 3.0 V interface support • Single-ended clock (CK) - 11 bus signals • Optional differential clock (CK, CK#) - 12 bus signals - Chip select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional read-write data strobe | Infineon 英飞凌 | | ||
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) HYPERBUS™ interface, 1.8 V/3.0 V Features • Interface - HYPERBUS™ interface - 1.8 V / 3.0 V interface support • Single-ended clock (CK) - 11 bus signals • Optional differential clock (CK, CK#) - 12 bus signals - Chip select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional read-write data strobe | Infineon 英飞凌 | | ||
HyperRAM (Self-Refresh DRAM) 3.0 V/1.8 V, 128-Mbit, Automotive-E (Grade 1) Features Interface • HyperBus Interface • 1.8 V / 3.0 V interface support - Single-ended clock (CK) - 11 bus signals - Optional differential clock (CK, CK#) - 12 bus signals • Chip Select (CS#) • 8-bit data bus (DQ[7:0]) • Hardware reset (RESET#) • Bidirectional Read-Write Data Strobe (RW | Infineon 英飞凌 | | ||
HyperRAM (Self-Refresh DRAM) 3.0 V/1.8 V, 128-Mbit, Automotive-E (Grade 1) Features Interface • HyperBus Interface • 1.8 V / 3.0 V interface support - Single-ended clock (CK) - 11 bus signals - Optional differential clock (CK, CK#) - 12 bus signals • Chip Select (CS#) • 8-bit data bus (DQ[7:0]) • Hardware reset (RESET#) • Bidirectional Read-Write Data Strobe (RW | Infineon 英飞凌 | | ||
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) HYPERBUS™ interface, 1.8 V/3.0 V Features • Interface - HYPERBUS™ interface - 1.8 V / 3.0 V interface support • Single-ended clock (CK) - 11 bus signals • Optional differential clock (CK, CK#) - 12 bus signals - Chip select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional read-write data strobe | Infineon 英飞凌 | | ||
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) HYPERBUS™ interface, 1.8 V/3.0 V Features • Interface - HYPERBUS™ interface - 1.8 V / 3.0 V interface support • Single-ended clock (CK) - 11 bus signals • Optional differential clock (CK, CK#) - 12 bus signals - Chip select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional read-write data strobe | Infineon 英飞凌 | | ||
Silicon Standard Recovery Diode 文件：646.62 Kbytes Page：3 Pages | GENESIC | | ||
Silicon Standard Recovery Diode 文件：805.37 Kbytes Page：3 Pages | GENESIC | | ||
Highest Flux Pure Green 文件：206.03 Kbytes Page：3 Pages | HB | | ||
HYPERBUS™ Memory | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
PSRAM — 伪静态RAM | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
封装/外壳：24-VBGA 包装：卷带（TR） 描述：IC PSRAM 128MBIT HYPERBUS 24FBGA 集成电路（IC） 存储器 | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
Silicon Standard Recovery Diode 文件：631.22 Kbytes Page：3 Pages | GENESIC | | ||
Silicon Standard Recovery Diode 文件：646.62 Kbytes Page：3 Pages | GENESIC | | ||
Silicon Standard Recovery Diode 文件：805.37 Kbytes Page：3 Pages | GENESIC | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | | ||
128Mb HYPERRAM??self-refresh DRAM(PSRAM) 文件：1.22054 Mbytes Page：57 Pages | Infineon 英飞凌 | |
S70K产品属性
- 类型
描述
- 型号
S70K
- 功能描述
整流器 800V 70A Std. Recovery
- RoHS
否
- 制造商
Vishay Semiconductors
- 产品
Standard Recovery Rectifiers
- 反向电压
100 V
- 恢复时间
1.2 us
- 正向连续电流
2 A
- 最大浪涌电流
35 A 反向电流
- IR
5 uA
- 安装风格
SMD/SMT
- 封装/箱体
DO-221AC
- 封装
Reel
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
CYPRESS/赛普拉斯 |
20+ |
MCP-24 |
25000 |
||||
SPANSION(飞索) |
25+ |
原装 |
25720 |
原装进口正品 |
|||
SPANSION/飞索半导体 |
24+ |
BGA |
8540 |
只做原装正品现货或订货假一赔十! |
|||
INFINEON |
23+ |
K-W |
6760 |
只有原装,请来电咨询 |
|||
GeneSiC Semiconductor |
25+ |
DO-5 |
9350 |
独立分销商 公司只做原装 诚心经营 免费试样正品保证 |
|||
CYPRESS/赛普拉斯 |
24+ |
MCP-24 |
39900 |
只做原装进口现货 |
|||
MCC |
24+ |
MODULE |
2100 |
公司大量全新现货 随时可以发货 |
|||
Cypress |
25+ |
25000 |
原厂原包 深圳现货 主打品牌 假一赔百 可开票! |
||||
SPANSION(飞索) |
2021+ |
FBGA-24(6x8) |
499 |
||||
CYPRESS(赛普拉斯) |
24+ |
BGA-24 |
2669 |
特价优势库存质量保证稳定供货 |
S70K规格书下载地址
S70K参数引脚图相关
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- sig
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- S7125AM
- S7125
- S7123SF
- S7123F
- S7123AM
- S7123
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- S711VB1
- S711VA1
- S711HB1
- S711HA1
- S70YR
- S70WS512N00BAWA33
- S70WS512N00BAWA32
- S70WS512N00BAWA30
- S70WS512N00BAWA23
- S70WS512N00BAWA22
- S70WS512N00BAWA20
- S70WS512N00
- S70VR
- S70V_16
- S70V
- S70TS
- S70T
- S70QR
- S70Q
- S70PT4
- S70NW6C
- S70MR
- S70M
- S-70L41B
- S70KR
- S70KG2C
- S70K_16
- S70JR
- S70J
- S70I
- S70GY9C
- S70GR2C
- S70GR
- S70GL-P
- S70GL256M00FFIIRD0
- S70GL256M00FFIIRC0
- S70GL256M00FFIIRB0
- S70GL256M00FFIIRA0
- S70GL256M00FAIIRD0
- S70GL256M00FAIIRC0
- S70GL256M00FAIIRB0
- S70GL256M00FAIIRA0
- S70GL256M00
- S70GL02GS12FHIV20
- S70GL02GS11FHI020
- S70GL02GS11FHI010
- S70GL02GP13FFIV23
- S70GB7C
- S70DR
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- S7077
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- S7070
- S7067
- S7063
- S7056
- S7055
- S7053
- S7052
S70K数据表相关新闻
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2023-3-31S7B-ZR-SM4A-TF(LF)(SN) JST连接器 表面贴装，直角 7 位置 0.059"（1.50mm）
针座连接器 表面贴装，直角 7 位置 0.059"（1.50mm）
2021-9-4S6B-ZR-SM4A-TF(LF)(SN) 针座jst连接器 表面贴装，直角 6 位置 0.059"（1.50mm）
S6B-ZR-SM4A-TF(LF)(SN)，针座连接器，表面贴装连接器
2021-7-30S78L05-正电压稳压器
说明 这一系列固定电压的单片集成电路电压调节器是专为广泛的应用。这些应用包括卡上消除监管噪音和分配问题与单点的监管。此外，他们可用于电通元素，使高电流的稳压器。每个这些稳压器能够提供的输出电流百毫安。内部限制和这些稳压器的热关断功能，使他们基本上不受超载。当齐纳二极管，电阻器的替代品使用，有效连同情人偏置电流可改善输出阻抗。 特点 •3端稳压器 •输出电流高达100mA •没有外部元件 •内部热过载保护 •内部短路限制
2013-1-13
DdatasheetPDF页码索引
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