Features

■ 32-bit RXv2 CPU core

 Max. operating frequency: 120 MHz

Capable of 240 DMIPS in operation at 120 MHz

 Single precision 32-bit IEEE-754 floating point

 Two types of multiply-and-accumulation unit (between memories

and between registers)

 32-bit multiplier (fastest instruction execution takes one CPU clock

cycle)

 Divider (fastest instruction execution takes two CPU clock cycles)

 Fast interrupt

 CISC Harvard architecture with 5-stage pipeline

 Variable-length instructions: Ultra-compact code

 Supports the memory protection unit (MPU)

 JTAG and FINE (one-line) debugging interfaces

■ Low-power design and architecture

 Operation from a single 2.7- to 3.6-V supply

 Low power consumption: A product that supports all peripheral

functions draws only 0.19 mA/MHz (Typ.).

 RTC is capable of operation from a dedicated power supply.

 Four low-power modes

■ On-chip code flash memory

 2 Mbytes of ROM

 No wait cycles at up to 50 MHz or when the ROM cache is hit, onewait

state at up to 100 MHz, two-wait state at above 100 MHz

 User code is programmable by on-board programming.

 Programming/erasing as background operations (BGOs)

 A dual-bank structure allows exchanging the start-up bank.

■ On-chip data flash memory

 32 Kbytes, reprogrammable up to 100,000 times

 Programming/erasing as background operations (BGOs)

■ On-chip SRAM, no wait states

 640 Kbytes of SRAM (no wait states)

 8 Kbytes of standby RAM (backup on deep software standby)