Features

The architecture enables:

• Efficient power transmission with accurate

digital programmability of RF carrier and

modulation shape

• EMC filter removal due to sinewave output

driver and Direct Antenna Connection (DiRAC)

• -80dBc RX sensitivity with full dynamic range

due to DiRAC

• SDK composed of FW and SW integrated in a

Split Stack architecture with PTX100R firmware

update capability over the host processor:

- Modular SW stack running on the Host

architecture

- Integrated FW running on the on-chip MCU

for time-critical operations

• Fractional-N PLL to support any reference input

clock frequency from 13.15MHz to 52MHz

• EMVCo® 3.0/3.1 PCD L1 compliancy2