Features

• Generates a T1 (1.544 MHz) or E1 (2.048 MHz) output

clock from an 8kHz frame clock input

• Configurable jitter attenuation characteristics, excellent

for use as a Stratum source de-jitter circuit

• VCXO-based clock generation ensures very low jitter and

phase noise generation

• Output clock is phase and frequency locked to the input

reference clock

• +115ppm minimum crystal frequency pullability range,

using recommended crystal

• Industrial temperature range

• Low power CMOS technology

• 16 pin TSSOP package

• Single 3.3 V power supply