Features

• Long-term output jitter <2 nsec over 10 μsec period

• External PLL clock feedback path enable “zero delay” I/O

clock skew configuration

• Selectable internal feedback divider provides popular

telecom and video clock frequencies (see tables below)

• Can optionally use external feedback divider to generate

other output frequencies.

• Single 3.3 V supply, low-power CMOS

• Power-down mode and output tri-state (pin OE)

• Packaged in 16-pin TSSOP

• Pb (lead) free package

• Industrial temperature range available