Product Description/Features:

• Low skew, low jitter PLL clock driver

• Max frequency supported = 266MHz (DDR 533)

• I2

C for functional and output control

• Feedback pins for input to output synchronization

• Spread Spectrum tolerant inputs

• 3.3V tolerant CLK_INT input

Switching Characteristics:

• CYCLE - CYCLE jitter (66MHz): <120ps

• CYCLE - CYCLE jitter (>100MHz): <65ps

• CYCLE - CYCLE jitter (>200MHz): <75ps

• OUTPUT - OUTPUT skew: <100ps

• DUTY CYCLE: 49.5 - 50.5