• LP-HCSL outputs save 8 resistors; minimal board space and BOM cost

• 53mW typical power consumption in PLL mode; minimal

power consumption

• OE# pins; support DIF power management

• HCSL compatible differential input; can be driven by

common clock sources

• Programmable Slew rate for each output; allows tuning

for various line lengths

• Programmable output amplitude; allows tuning for

various application environments

• Pin/software selectable PLL bandwidth and PLL Bypass;

minimize phase jitter for each application

• Outputs blocked until PLL is locked; clean system start-up

• Software selectable 50MHz or 125MHz PLL operation;

useful for Ethernet applications

• Configuration can be accomplished with strapping pins;

SMBus interface not required for device control

• 3.3V tolerant SMBus interface works with legacy controllers

• Space saving 5 x 5mm 32-VFQFPN; minimal board space

• Selectable SMBus addresses; multiple devices can

easily share an SMBus segment