Description

The 9DBV0241 is a member of Renesas' 1.8V

Very-Low-Power (VLP) PCIe family. The device has 2 output

enables for clock management.

Features/Benefits

• LP-HCSL outputs with Zo = 100; saves 8 resistors

compared to standard HCSL outputs

• 35mW typical power consumption in PLL mode; reduced

thermal concerns

• Spread Spectrum (SS) compatible; allows use of SS for

EMI reduction

• OE# pins; support DIF power management

• HCSL compatible differential input; can be driven by

common clock sources

• SMBus-selectable features; optimize signal integrity to

application

• slew rate for each output

• differential output amplitude

• Pin/software selectable PLL bandwidth and PLL Bypass;

optimize PLL to application

• Outputs blocked until PLL is locked; clean system start-up

• Device contains default configuration; SMBus interface not

required for device control

• 3.3V tolerant SMBus interface; works with legacy

controllers

• Space saving 4 × 4mm 24-VFQFPN; minimal board space