FEATURES

• Two divide by 1 differential 3.3V LVPECL outputs;

Two divide by 2 differential 3.3V LVPECL outputs

• Selectable differential CLK, nCLK or LVPECL clock inputs

• CLK, nCLK pair can accept the following differential

input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

• PCLK, nPCLK supports the following input types:

LVPECL, CML, SSTL

• Maximum output frequency: 650MHz

• Translates any single ended input signal (LVCMOS, LVTTL,

GTL) to LVPECL levels with resistor bias on nCLK input

• Output skew: 75ps (maximum)

• Part-to-part skew: 300ps (maximum)

• Bank skew: Bank A - 30ps (maximum)

Bank B - 45ps (maximum)

• 3.3V operating supply

• -40°C to 85°C ambient operating temperature

• Available in lead-free RoHS-compliant package