Features

• 1:2 differential data/clock fanout buffer and line driver

• 4.5 Gbps data rate (NRZ) (maximum)

• Differential LVDS outputs

• Differential input supporting LVDS, LVPECL and CML levels

• Configurable output pre-emphasis

• Low-skew outputs: 10ps (maximum)

• Low data deterministic jitter: 4ps (maximum)

• LVCMOS interface levels for the control inputs

• Asynchronous output disable into high-impedance state

• Internal input termination: 100(Differential)

• Additive phase jitter, RMS: 0.08ps (typical)

• Full 3.3V supply voltage

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package