Features

• Two programmable differential LVDS or LVPECL output banks

• Two differential clock input pairs

• PCLKx, nPCLKx pairs can accept the following differential

input levels: LVDS, LVPECL, SSTL, CML

• Maximum output frequency: 3GHz

• Translates any single ended input signal to LVDS levels with

resistor bias on nPCLKx inputs

• Output skew: 15ps (maximum)

• Bank skew: 15ps (maximum)

• Propagation delay: 500ps (maximum)

• Additive phase jitter, RMS: 0.15ps (typical)

• Full 3.3V or 2.5V supply modes

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package