Features

• Twelve LVCMOS/LVTTL outputs

• Selectable differential CLK/nCLK or LVCMOS/LVTTL clock input

• CLK/nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• LVCMOS_CLK supports the following input types:

LVCMOS, LVTTL

• Output frequency: 350MHz

• Additive phase jitter, RMS: 0.14ps (typical)

• Output skew: 100ps (maximum), 3.3V±5

• Part-to-part skew: 1ns (maximum), 3.3V±5

• Operating supply modes:

• Core/Output

3.3V/3.3V

3.3V/2.5V

2.5V/2.5V

• -40°C to 85°C ambient operating temperature

• Lead-free (RoHS 6) packaging