FEATURES

• Twelve LVCMOS outputs

• Selectable LVCMOS clock or differential CLK, nCLK inputs

• CLK, nCLK pair can accept the following differential

input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

• LVCMOS_CLK accepts the following input levels:

LVCMOS or LVTTL

• Maximum output frequency: 150MHz

• Output skew: 350ps (maximum)

• Part to part skew: 1.5ns (maximum)

• 3.3V core, 3.3V output

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package