Features

• Two LVCMOS/LVTTL outputs

• Differential CLK/nCLK input pair

• CLK/nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Output frequency: 350MHz (typical)

• Output skew: 20ps (maximum)

• Part-to-part skew: 600ps (maximum)

• Additive phase jitter, RMS: 0.092ps (typical)

• Small 8 lead SOIC package saves board space

• Full 3.3V operating supply

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package