Features

• 25-bit 1:1 or 14-bit 1:2 registered buffer with parity check

functionality

• Supports SSTL_18 JEDEC specification on data inputs

and outputs

• Supports LVCMOS switching levels on C0, C1, and

RESET inputs

• Low voltage operation: VDD = 1.7V to 1.9V

• Available in 96-ball LFBGA package

Applications

• DDR2 Memory Modules

• Provides complete DDR DIMM solution with

ICS98ULPA877A or IDTCSPUA877A

• Ideal for DDR2 667 and 800