Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator

General Description The RT9173D is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requ

Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator

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Digital Subscriber Interface Circuit with RxSB

Description The MT9173 (DSIC) and MT9174 (DNIC) are functionally identical to the MT9171/72 except for the addition of one feature. The MT9173/74 include a digital output pin indicating the temporal position of the received SYNC bit of the biphase transmission. This feature is especially useful

Digital Subscriber Interface Circuit with RxSB

Description The MT9173 (DSIC) and MT9174 (DNIC) are functionally identical to the MT9171/72 except for the addition of one feature. The MT9173/74 include a digital output pin indicating the temporal position of the received SYNC bit of the biphase transmission. This feature is especially useful

Digital Subscriber Interface Circuit with RxSB

Description The MT9173 (DSIC) and MT9174 (DNIC) are functionally identical to the MT9171/72 except for the addition of one feature. The MT9173/74 include a digital output pin indicating the temporal position of the received SYNC bit of the biphase transmission. This feature is especially useful

Digital Subscriber Interface Circuit with RxSB

Description The MT9173 (DSIC) and MT9174 (DNIC) are functionally identical to the MT9171/72 except for the addition of one feature. The MT9173/74 include a digital output pin indicating the temporal position of the received SYNC bit of the biphase transmission. This feature is especially useful

Quad LVDS Line Receiver with Flow-Through Pinout and ?쏧n-Path??Fail-Safe

文件：277.96 Kbytes Page：14 Pages