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PCD5002中文资料

厂家型号

PCD5002

文件大小

203.79Kbytes

页面数量

48

功能描述

Advanced POCSAG and APOC-1 Paging Decoder

Telecommunication Decoder

数据手册

下载地址一下载地址二

生产厂商

PHI

PCD5002数据手册规格书PDF详情

GENERAL DESCRIPTION

The PCD5002 is a very low power pager decoder and controller, capable of handling both standard POCSAG and the advanced APOC-1 code. Continuous data decoding upon reception of a dedicated sync word is available for news pager applications.

Data rates supported are 512, 1200 and 2400 bits/s using a single 76.8 kHz crystal. On-chip EEPROM is programmable using a minimum supply voltage of 2.0 V, allowing ‘over-the-air’ programming. I2C-bus compatible.

FEATURES

• Wide operating supply voltage range: 1.5 to 6.0 V

• EEPROM programming requires only 2.0 V supply

• Low operating current: 50 µA typ. (ON), 25 µA typ. (OFF)

• Temperature range −25 to +70 °C

• “CCIR radio paging Code No. 1” (POCSAG) compatible

• Supports Advanced Pager Operator’s Code Phase 1 (APOC-1) for extended battery economy

• 512, 1200 and 2400 bits/s data rates using 76.8 kHz crystal

• Built-in data filter (16-times oversampling) and bit clock recovery

• Advanced ACCESS synchronization algorithm

• 2-bit random and (optional) 4-bit burst error correction

• Up to 6 user addresses (RICs), each with 4 functions/alert cadences

• Up to 6 user address frames, independently programmable

• Standard POCSAG sync word, plus up to 4 user programmable sync words

• Continuous data decoding upon reception of user programmable sync word (optional)

• Received data inversion (optional)

• Call alert via beeper, vibrator or LED

• 2-level acoustic alert using single external transistor

• Alert control: automatic (POCSAG type), via cadence register or alert input pin

• Separate power control of receiver and RF oscillator for battery economy

• Synthesizer set-up and control interface (3-line serial)

• On-chip EEPROM for storage of user addresses (RICs), pager configuration and synthesizer data

• On-chip SRAM buffer for message data

• Slave I2C-bus interface to microcontroller for transfer of message data, status/control and EEPROM programming (data transfer at up to 100 kbits/s)

• Wake-up interrupt for microcontroller, programmable polarity

• Direct and I2C-bus control of operating status (ON/OFF)

• Battery-low indication (external detector)

• Out-of-range condition indication

• Real time clock reference output

• On-chip voltage doubler

• Interfaces directly to UAA2080 and UAA2082 paging receivers.

APPLICATIONS

• Advanced display pagers (POCSAG and APOC-1)

• Basic alert-only pagers

• Information services

• Personal organizers

• Telepoint

• Telemetry/data transmission.

PCD5002产品属性

  • 类型

    描述

  • 型号

    PCD5002

  • 功能描述

    Telecommunication Decoder

更新时间:2025-12-2 15:01:00
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