Single, dual and triple output 1 to 10.5 Watt AC/DC encapsulated modules

文件：65.97 Kbytes Page：3 Pages

网络控制器与处理器 IC 2x10G + 16xSFP multi-rate, multi-protocol over OTN/SONET/SDH PHY

功能：- 包装：托盘 描述：2X10G + 16XSFP MULTI-RATE, MULTI 集成电路（IC） 控制器

功能：- 包装：托盘 描述：2X10G + 16XSFP MULTI-RATE, MULTI 集成电路（IC） 控制器

HyPHY-10G OTN Processor

1X10G + 1X10G/8XSFP MULTI-RATE,

Single, dual and triple output 1 to 10.5 Watt AC/DC encapsulated modules

文件：46.83 Kbytes Page：2 Pages

Single, dual and triple output 1 to 10.5 Watt AC/DC encapsulated modules

文件：65.97 Kbytes Page：3 Pages

Single, dual and triple output 1 to 10.5 Watt AC/DC encapsulated modules

文件：65.97 Kbytes Page：3 Pages

TREK 542A

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CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b