位置：首页 > IC中文资料第8575页 > PLL103
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
Low Skew Buffers FEATURES • Generate 18 copies of High-speed clock inputs. • Supports up to four SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin f | PLL |   | ||
Low Skew Buffers FEATURES • Generate 18 copies of High-speed clock inputs. • Supports up to four SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin f | PLL | | ||
Low Skew Buffers FEATURES • Generate 18 copies of High-speed clock inputs. • Supports up to four SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin f | PLL | | ||
Low Skew Buffers FEATURES • Generate 18 copies of High-speed clock inputs. • Supports up to four SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin f | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS [PLL] DESCRIPTIONS The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02 | ETCList of Unclassifed Manufacturers 未分类制造商 | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS [PLL] DESCRIPTIONS The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02 | ETCList of Unclassifed Manufacturers 未分类制造商 | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS [PLL] DESCRIPTIONS The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02 | ETCList of Unclassifed Manufacturers 未分类制造商 | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS [PLL] DESCRIPTIONS The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02 | ETCList of Unclassifed Manufacturers 未分类制造商 | | ||
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and | PLL | | ||
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and | PLL | | ||
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and | PLL | | ||
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and | PLL | | ||
1-to-4 Clock Distribution Buffer DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out | PLL | | ||
1-to-4 Clock Distribution Buffer DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out | PLL | | ||
1-to-4 Clock Distribution Buffer DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out | PLL | | ||
1-to-4 Clock Distribution Buffer DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out | PLL | | ||
1-to-5 Clock Distribution Buffer DESCRIPTIONS The PLL103-05 is a 1-to-5 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 5 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. FEATURES • 5 outputs identical to FIN. • Low skew ( | PLL | | ||
1-to-5 Clock Distribution Buffer DESCRIPTIONS The PLL103-05 is a 1-to-5 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 5 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. FEATURES • 5 outputs identical to FIN. • Low skew ( | PLL | | ||
1-to-5 Clock Distribution Buffer DESCRIPTIONS The PLL103-05 is a 1-to-5 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 5 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. FEATURES • 5 outputs identical to FIN. • Low skew ( | PLL | | ||
1-to-5 Clock Distribution Buffer DESCRIPTIONS The PLL103-05 is a 1-to-5 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 5 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. FEATURES • 5 outputs identical to FIN. • Low skew ( | PLL | | ||
DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS DESCRIPTIONS The PLL103-06 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 DDR DIMMS. The PLL103-06 can be used in conjunction with | PLL | | ||
DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS DESCRIPTIONS The PLL103-06 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 DDR DIMMS. The PLL103-06 can be used in conjunction with | PLL | | ||
DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS DESCRIPTIONS The PLL103-06 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 DDR DIMMS. The PLL103-06 can be used in conjunction with | PLL | | ||
DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS DESCRIPTIONS The PLL103-06 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 DDR DIMMS. The PLL103-06 can be used in conjunction with | PLL | | ||
2 DIMM DDR Fanout Buffer DESCRIPTIONS The PLL103-07 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 2 DDR DIMMs. The PLL103-07 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 2 | PLL | | ||
2 DIMM DDR Fanout Buffer DESCRIPTIONS The PLL103-07 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 2 DDR DIMMs. The PLL103-07 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 2 | PLL | | ||
2 DIMM DDR Fanout Buffer DESCRIPTIONS The PLL103-07 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 2 DDR DIMMs. The PLL103-07 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 2 | PLL | | ||
2 DIMM DDR Fanout Buffer DESCRIPTIONS The PLL103-07 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 2 DDR DIMMs. The PLL103-07 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 2 | PLL | | ||
Low Skew Buffers FEATURES • Generates 13 copies of High-speed clock inputs. • Supports up to three SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin | PLL | | ||
Low Skew Buffers FEATURES • Generates 13 copies of High-speed clock inputs. • Supports up to three SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin | PLL | | ||
Low Skew Buffers FEATURES • Generates 13 copies of High-speed clock inputs. • Supports up to three SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin | PLL | | ||
Low Skew Buffers FEATURES • Generates 13 copies of High-speed clock inputs. • Supports up to three SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin | PLL | | ||
DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS DESCRIPTIONS The PLL103-53 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 30 outputs. These outputs can be configured to support 4 unbuffered DDR (Double Data Rate) DIMMS or to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 D | PLL | | ||
DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS DESCRIPTIONS The PLL103-53 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 30 outputs. These outputs can be configured to support 4 unbuffered DDR (Double Data Rate) DIMMS or to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 D | PLL | | ||
DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS DESCRIPTIONS The PLL103-53 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 30 outputs. These outputs can be configured to support 4 unbuffered DDR (Double Data Rate) DIMMS or to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 D | PLL | | ||
DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS DESCRIPTIONS The PLL103-53 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 30 outputs. These outputs can be configured to support 4 unbuffered DDR (Double Data Rate) DIMMS or to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 D | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS | PLL | | ||
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS | PLL | | ||
1-to-4 Clock Distribution Buffer | PLL | | ||
D챕tails complets sur le site du fabricant: IDEAL # 103 (103) Description du produit Détails complets sur le site du fabricant: IDEAL INDUSTRIES, INC | DBLECTRO | | ||
0.1/2.5 GHz Si MMIC BUFFER AMPLIFIERS DESCRIPTION The STB7102, STB7103 and STB7104 designed for Mobile Phone applications (0.1/2.5GHz), are an high isolation Si MMIC Buffer Amplifiers. Manufactured in the third generation of ST proprietary bipolar process, they offers an excellent isolation and a good linearity using a low current co | STMICROELECTRONICS 意法半导体 | | ||
Customer Specification Construction Diameters (In) 1) Component 1 8 X 1 COND a) Conductor 24 (19/36) AWG Bare Copper 0.025 b) Insulation 0.011 Wall, Nom. PVC, Semi Rigid 0.047 (1) Color(s) Cond Color Cond Color Cond Color 1 WHITE 4 YELLOW 7 BLUE 2 BROWN 5 SLATE 8 RED 3 GREEN 6 PINK 2) Cable Assembly 8 Componen | ALPHAWIRE | | ||
Customer Specification Construction Diameters (In) 1) Component 1 8 X 1 COND a) Conductor 24 (19/36) AWG Bare Copper 0.025 b) Insulation 0.011 Wall, Nom. PVC, Semi Rigid 0.047 (1) Color(s) Cond Color Cond Color Cond Color 1 WHITE 4 YELLOW 7 BLUE 2 BROWN 5 SLATE 8 RED 3 GREEN 6 PINK 2) Cable Assembly 8 Componen | ALPHAWIRE | | ||
Smooth, high torque, roller ratchet handle 文件：254.3 Kbytes Page：3 Pages | ETCList of Unclassifed Manufacturers 未分类制造商 | |
PLL103产品属性
- 类型
描述
- 型号
PLL103
- 制造商
PLL
- 制造商全称
PLL
- 功能描述
Low Skew Buffers
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
PHASELI |
24+ |
SSOP48 |
8000 |
只做自己库存 全新原装进口正品假一赔百 可开13%增 |
|||
PHASELIN |
24+ |
NA/ |
30 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
|||
PHASELIN |
22+ |
SSOP48 |
20000 |
公司只做原装 品质保障 |
|||
PHASELI |
25+ |
SSOP48 |
30 |
百分百原装正品 真实公司现货库存 本公司只做原装 可 |
|||
23+ |
BGAQFP |
8659 |
原装公司现货!原装正品价格优势. |
||||
PHASELINK |
25+23+ |
SSOP |
36452 |
绝对原装正品全新进口深圳现货 |
|||
PLL |
23+ |
SSOP |
360000 |
原厂授权一级代理,专业海外优势订货,价格优势、品种 |
|||
PHASELIN |
22+ |
SSOP48 |
5000 |
全新原装现货!自家库存! |
|||
25+ |
SSOP |
2700 |
全新原装自家现货优势! |
||||
24+ |
SSOP |
17 |
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PLL103规格书下载地址
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DdatasheetPDF页码索引
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