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PLL价格
参考价格：￥0.1956
型号：PLL-14-Y2-10 品牌：Panduit 备注：这里有PLL多少钱，2025年最近7天走势，今日出价，今日竞价，PLL批发/采购报价，PLL行情走势销售排行榜，PLL报价。| 型号 | 功能描述 | 生产厂家&企业 | LOGO | 操作 |
|---|---|---|---|---|
PHASE LOCKED LOOP FEATURES • Frequency Range: 200 - 230 MHz • Step Size: 100 KHz • PLL - Style Package APPLICATIONS • Telecommunications • Satellite • Telemetry | ZCOMM |   | ||
PHASE LOCKED LOOP [Z-Communications, Inc.] FEATURES • Frequency Range: 900 - 960 MHz • Step Size: 100 KHz • PLL - Style Package APPLICATIONS • Basestations • Mobile Radios • Satellite Communications | ETCList of Unclassifed Manufacturers 未分类制造商 | | ||
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | Altera 阿尔特 | | ||
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | Altera 阿尔特 | | ||
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | Altera 阿尔特 | | ||
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | Altera 阿尔特 | | ||
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | Altera 阿尔特 | | ||
PHASE LOCKED LOOP [Z-Communications, Inc.] FEATURES • Frequency Range: 988 - 1028 MHz • Step Size: 1000 KHz • PLL - Style Package APPLICATIONS • Basestations • Mobile Radios • Satellite Communications | ETCList of Unclassifed Manufacturers 未分类制造商 | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the | PLL | | ||
Low Skew Output Buffer DESCRIPTIONS The PLL102-15 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8 -pin SOIC or TSSOP package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feedback to t | PLL | | ||
Low Skew Output Buffer DESCRIPTIONS The PLL102-15 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8 -pin SOIC or TSSOP package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feedback to t | PLL | | ||
Low Skew Buffers FEATURES • Generate 18 copies of High-speed clock inputs. • Supports up to four SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin f | PLL | | ||
Low Skew Buffers FEATURES • Generate 18 copies of High-speed clock inputs. • Supports up to four SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin f | PLL | | ||
Low Skew Buffers FEATURES • Generate 18 copies of High-speed clock inputs. • Supports up to four SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin f | PLL | | ||
Low Skew Buffers FEATURES • Generate 18 copies of High-speed clock inputs. • Supports up to four SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin f | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS [PLL] DESCRIPTIONS The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02 | ETC1List of Unclassifed Manufacturers etc未分类制造商未分类制造商 | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS [PLL] DESCRIPTIONS The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02 | ETC1List of Unclassifed Manufacturers etc未分类制造商未分类制造商 | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS [PLL] DESCRIPTIONS The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02 | ETC1List of Unclassifed Manufacturers etc未分类制造商未分类制造商 | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS [PLL] DESCRIPTIONS The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02 | ETC1List of Unclassifed Manufacturers etc未分类制造商未分类制造商 | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and | PLL | | ||
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and | PLL | | ||
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and | PLL | | ||
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and | PLL | | ||
1-to-4 Clock Distribution Buffer DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out | PLL | | ||
1-to-4 Clock Distribution Buffer DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out | PLL | | ||
1-to-4 Clock Distribution Buffer DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out | PLL | | ||
1-to-4 Clock Distribution Buffer DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out | PLL | |
PLL产品属性
- 类型
描述
- 型号
PLL
- 制造商
BOSCH
- 功能描述
LASER LEVEL PEN
- 制造商
Bosch Sensortec
- 功能描述
LASER LEVEL, PEN
- 制造商
Bosch Sensortec
- 功能描述
LASER LEVEL, PEN; Overall
- Length
140mm;
- SVHC
No SVHC(19-Dec-2012);
- Accuracy
1mm; Accuracy
- mm/Inch
1mm/m; Measuring Range
- Max
5m ;RoHS
- Compliant
NA
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
PHASELINK |
24+ |
NA/ |
1628 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
|||
PHASELINK |
2016+ |
SOP8 |
2500 |
只做原装,假一罚十,公司可开17%增值税发票! |
|||
Phaseli |
24+ |
SOP8 |
8000 |
只做自己库存 全新原装进口正品假一赔百 可开13%增 |
|||
PHASELINK |
22+ |
SOP8 |
5000 |
全新原装现货!自家库存! |
|||
Phaselink |
23+ |
SMD |
5000 |
原装正品,假一罚十 |
|||
PHASELI |
2447 |
SOP8 |
100500 |
一级代理专营品牌!原装正品,优势现货,长期排单到货 |
|||
ALTECH |
23+ |
原厂原包 |
19960 |
只做进口原装 终端工厂免费送样 |
|||
PHASELINK |
1923+ |
SOP-8 |
10000 |
只做原装特价 |
|||
ZCOMM |
24+ |
SMD |
1680 |
ZCOMM专营品牌进口原装现货假一赔十 |
|||
Phaselink |
0608+ |
SOP8 |
1628 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
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