PIC18F46K22价格

参考价格:¥22.8961

型号:PIC18F46K22-E/ML 品牌:Microchip 备注:这里有PIC18F46K22多少钱,2025年最近7天走势,今日出价,今日竞价,PIC18F46K22批发/采购报价,PIC18F46K22行情走势销售排行榜,PIC18F46K22报价。
型号 功能描述 生产厂家 企业 LOGO 操作
PIC18F46K22

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

PIC18F46K22

Flash Memory Programming Specification

文件:545.77 Kbytes Page:42 Pages

Microchip

微芯科技

PIC18F46K22

Newer Device Available PIC18F46Q10

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operatio

Microchip

微芯科技

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

文件:5.67499 Mbytes Page:496 Pages

Microchip

微芯科技

PIC18F46K22产品属性

  • 类型

    描述

  • 型号

    PIC18F46K22

  • 功能描述

    8位微控制器 -MCU 64KB Flash 3968B RAM 8b FamilynanoWat XLP

  • RoHS

  • 制造商

    Silicon Labs

  • 核心

    8051

  • 处理器系列

    C8051F39x

  • 数据总线宽度

    8 bit

  • 最大时钟频率

    50 MHz

  • 程序存储器大小

    16 KB 数据 RAM

  • 大小

    1 KB 片上

  • ADC

    Yes

  • 工作电源电压

    1.8 V to 3.6 V

  • 工作温度范围

    - 40 C to + 105 C

  • 封装/箱体

    QFN-20

  • 安装风格

    SMD/SMT

更新时间:2025-9-28 18:12:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
NA
23+
NA
26094
10年以上分销经验原装进口正品,做服务型企业
MICROCHIP/微芯
24+
TQFP-44
8000
原装,正品
MICROCHIP/微芯
25+
25000
原厂原包 深圳现货 主打品牌 假一赔百 可开票!
MICROCHIP/微芯
2450+
QFP
8850
只做原装正品假一赔十为客户做到零风险!!
MICROCHIP
25+
QFNEP
3000
全新原装、诚信经营、公司现货销售!
MICROCHIP/?о
25+
QFN
10000
原装,请咨询
Microchip Technology
23+
40-DIP
11200
主营:汽车电子,停产物料,军工IC
MICROCHIP原装现货特价
QFP
500
原装长期供货!
Microchip/微芯
22+
QFN
6000
只做原装,公司现货,提供一站式BOM配单服务!
MicrochipTechnology
24+
原厂原装
6000
进口原装正品假一赔十,货期7-10天

PIC18F46K22数据表相关新闻