封装/外壳：56-TFSOP（0.240"，6.10mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC UNIV BUS DVR 18BIT 56TSSOP 集成电路（IC） 通用总线功能

封装/外壳：56-TFSOP（0.240"，6.10mm 宽） 包装：管件 描述：IC UNIV BUS DVR 18BIT 56TSSOP 集成电路（IC） 通用总线功能

18-bit registered driver with inverted register enable 3-State

DESCRIPTION The 74AVC16834 is a 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance state

18-bit registered driver with inverted register enable and Dynamic Controlled Outputs (3-State)

DESCRIPTION The 74AVC16834A is a 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance stat

18-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state

1. General description The 74AVC16834A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-

18-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state

1. General description The 74AVC16834A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-

18-bit registered driver with inverted register enable and Dynamic Controlled Outputs (3-State)

DESCRIPTION The 74AVC16834A is a 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance stat