Zero-Delay Clock Buffer

Description The PI6C2404A-1 is a PLL-based, zero-delay buffer, with the ability to distribute four outputs of up to 133 MHz at 3.3V. Two banks of two outputs exist, OUTA[1–2] and OUTB[1–2]. An external feedback pin is used to synchronize the outputs to the input; the relationship between loading

Zero-Delay Clock Buffer

Description The PI6C2404A-1 is a PLL-based, zero-delay buffer, with the ability to distribute four outputs of up to 133 MHz at 3.3V. Two banks of two outputs exist, OUTA[1–2] and OUTB[1–2]. An external feedback pin is used to synchronize the outputs to the input; the relationship between loading

Zero-Delay Clock Buffer

Description The PI6C2404A-1 is a PLL-based, zero-delay buffer, with the ability to distribute four outputs of up to 133 MHz at 3.3V. Two banks of two outputs exist, OUTA[1–2] and OUTB[1–2]. An external feedback pin is used to synchronize the outputs to the input; the relationship between loading

Zero-Delay Clock Buffer

Description The PI6C2404A-1 is a PLL-based, zero-delay buffer, with the ability to distribute four outputs of up to 133 MHz at 3.3V. Two banks of two outputs exist, OUTA[1–2] and OUTB[1–2]. An external feedback pin is used to synchronize the outputs to the input; the relationship between loading

Zero-Delay Clock Buffer

Description The PI6C2404A-1 is a PLL-based, zero-delay buffer, with the ability to distribute four outputs of up to 133 MHz at 3.3V. Two banks of two outputs exist, OUTA[1–2] and OUTB[1–2]. An external feedback pin is used to synchronize the outputs to the input; the relationship between loading